From 7bf8a6df381a667134b55701993c6770d32bc76b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 11:56:55 -0800 Subject: Moved usrp2 fpga files into usrp2 subdir. --- usrp2/opencores/spi/rtl/verilog/CVS/Entries | 6 ++++++ usrp2/opencores/spi/rtl/verilog/CVS/Repository | 1 + usrp2/opencores/spi/rtl/verilog/CVS/Root | 1 + usrp2/opencores/spi/rtl/verilog/CVS/Template | 0 4 files changed, 8 insertions(+) create mode 100644 usrp2/opencores/spi/rtl/verilog/CVS/Entries create mode 100644 usrp2/opencores/spi/rtl/verilog/CVS/Repository create mode 100644 usrp2/opencores/spi/rtl/verilog/CVS/Root create mode 100644 usrp2/opencores/spi/rtl/verilog/CVS/Template (limited to 'usrp2/opencores/spi/rtl/verilog/CVS') diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Entries b/usrp2/opencores/spi/rtl/verilog/CVS/Entries new file mode 100644 index 000000000..d125a1657 --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/CVS/Entries @@ -0,0 +1,6 @@ +/spi_clgen.v/1.3/Thu Jul 3 17:32:15 2003// +/spi_defines.v/1.8/Mon Mar 15 17:46:08 2004// +/spi_shift.v/1.7/Tue Jul 8 15:36:37 2003// +/spi_top.v/1.8/Tue Jul 8 15:36:37 2003// +/timescale.v/1.1.1.1/Wed Jun 12 15:45:23 2002// +D diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Repository b/usrp2/opencores/spi/rtl/verilog/CVS/Repository new file mode 100644 index 000000000..361b93bf8 --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +spi/rtl/verilog diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Root b/usrp2/opencores/spi/rtl/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/rtl/verilog/CVS/Template b/usrp2/opencores/spi/rtl/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb -- cgit v1.2.3