From d4649caee02a1c76802dc4f8d7d76bb31b14ce09 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 16 Feb 2010 22:49:02 -0800
Subject: wishbone bridge now with minimal functionality.  Need to check timing
 and handle wait states.

---
 usrp2/models/gpmc_model.v | 70 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 usrp2/models/gpmc_model.v

(limited to 'usrp2/models')

diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
new file mode 100644
index 000000000..ce3acaacf
--- /dev/null
+++ b/usrp2/models/gpmc_model.v
@@ -0,0 +1,70 @@
+
+
+module gpmc_model
+  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   assign EM_CLK = 0;
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+   
+   initial
+     begin
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 #2;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #4;
+	 EM_NCS6 <= 0;
+	 #5;
+	 EM_NWE <= 0;
+	 #41;
+	 EM_NWE <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input [10:0] addr;
+      begin
+	 #2;
+	 EM_A <= addr[10:1];
+	 #4;
+	 EM_NCS6 <= 0;
+	 #5;
+	 EM_NOE <= 0;
+	 #41;
+	 EM_NOE <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 $display("Data Read from GPMC: %X",EM_D);
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(36,16'hBEEF);
+	#1000;
+	GPMC_Read(36);
+	#1000;
+	$finish;
+     end
+   
+endmodule // gpmc_model
-- 
cgit v1.2.3


From 1912ff60acd490a24204a7596e373e9aef9276cd Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 17 Feb 2010 15:00:41 -0800
Subject: speed up the presentation of registered wb data to the gpmc

---
 usrp2/gpmc/gpmc.v         |  7 +++++--
 usrp2/models/gpmc_model.v | 26 +++++++++++++++-----------
 2 files changed, 20 insertions(+), 13 deletions(-)

(limited to 'usrp2/models')

diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 1963af6e6..56f879abc 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -12,7 +12,7 @@ module gpmc
 
    wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
    wire [15:0] 	EM_D_ram;
-   reg [15:0] 	EM_D_wb;
+   wire [15:0] 	EM_D_wb;
 
    assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb;
 
@@ -44,10 +44,13 @@ module gpmc
 	  wb_sel_o <= ~EM_NBE;
        end
 
+   reg [15:0] EM_D_wb_reg;
    always @(posedge wb_clk)
      if(wb_ack_i)
-       EM_D_wb <= wb_dat_miso;
+       EM_D_wb_reg <= wb_dat_miso;
 
+   assign EM_D_wb = wb_ack_i ? wb_dat_miso : EM_D_wb_reg;
+   
    // stb, oe_del, we_del
    assign wb_cyc_o = wb_stb_o;
 
diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
index ce3acaacf..38dde1fa5 100644
--- a/usrp2/models/gpmc_model.v
+++ b/usrp2/models/gpmc_model.v
@@ -25,16 +25,18 @@ module gpmc_model
       input [10:0] addr;
       input [15:0] data;
       begin
-	 #2;
+	 #2.3;
 	 EM_A <= addr[10:1];
 	 EM_D_int <= data;
-	 #4;
+	 #2.01;
 	 EM_NCS6 <= 0;
-	 #5;
+	 #14;
 	 EM_NWE <= 0;
-	 #41;
-	 EM_NWE <= 1;
+	 #77.5;
 	 EM_NCS6 <= 1;
+	 //#1.5;
+	 EM_NWE <= 1;
+	 #6;
 	 EM_A <= 10'bz;
 	 EM_D_int <= 16'bz;
       end
@@ -43,17 +45,19 @@ module gpmc_model
    task GPMC_Read;
       input [10:0] addr;
       begin
-	 #2;
+	 #1.3;
 	 EM_A <= addr[10:1];
-	 #4;
+	 #3;
 	 EM_NCS6 <= 0;
-	 #5;
+	 #14;
 	 EM_NOE <= 0;
-	 #41;
-	 EM_NOE <= 1;
+	 #77.5;
 	 EM_NCS6 <= 1;
-	 EM_A <= 10'bz;
+	 //#1.5;
 	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254;
+	 EM_A <= 10'bz;
       end
    endtask // GPMC_Read
    
-- 
cgit v1.2.3


From 030f6a21539207c058b982ffade384ec7a937ec2 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 25 Feb 2010 16:50:09 -0800
Subject: First cut at passing data buffers around on GPMC bus

---
 usrp2/gpmc/dbsm.v         | 88 +++++++++++++++++++++++++++++++++++++++++++++++
 usrp2/gpmc/gpmc.v         | 45 ++++++++++++++++++------
 usrp2/models/gpmc_model.v | 23 ++++++++++---
 usrp2/top/u1e/tb_u1e.v    | 11 ++++--
 usrp2/top/u1e/u1e.v       |  3 +-
 usrp2/top/u1e/u1e_core.v  | 20 +++++++----
 6 files changed, 165 insertions(+), 25 deletions(-)
 create mode 100644 usrp2/gpmc/dbsm.v

(limited to 'usrp2/models')

diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v
new file mode 100644
index 000000000..0f27be46a
--- /dev/null
+++ b/usrp2/gpmc/dbsm.v
@@ -0,0 +1,88 @@
+
+module bsm
+  (input clk, input reset, input clear,
+   input write_done,
+   input read_done,
+   output readable,
+   output writeable);
+
+   reg 	  state;
+   localparam ST_WRITEABLE = 0;
+   localparam ST_READABLE = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= ST_WRITEABLE;
+     else
+       case(state)
+	 ST_WRITEABLE :
+	   if(write_done)
+	     state <= ST_READABLE;
+	 ST_READABLE :
+	   if(read_done)
+	     state <= ST_WRITEABLE;
+       endcase // case (state)
+
+   assign readable = (state == ST_READABLE);
+   assign writeable = (state == ST_WRITEABLE);
+   
+endmodule // bsm
+
+module dbsm
+  (input clk, input reset, input clear,
+   output reg read_sel, output read_ready, input read_done,
+   output reg write_sel, output write_ready, input write_done);
+
+   localparam NUM_BUFS = 2;
+
+   wire       [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf;
+   
+   // Two of these buffer state machines
+   genvar     i;
+   for(i=0;i<NUM_BUFS;i=i+1)
+     generate
+	bsm bsm(.clk(clk), .reset(reset), .clear(clear), 
+		.write_done((write_sel == i) & write_done), 
+		.read_done((read_sel == i) & read_done), 
+		.readable(readable[i]), .writeable(writeable[i]));
+     endgenerate
+   
+   reg 	 full;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  write_sel <= 0;
+	  full <= 0;
+       end
+     else
+       if(write_done)
+	 if(writeable[write_sel]==(NUM_BUFS-1))
+	   begin
+	      write_sel <= 0;
+	      if(read_sel == 0)
+		full <= 1;
+	   end
+	 else
+	   begin
+	      write_sel <= write_sel + 1;
+	      if(read_sel == write_sel + 1)
+		full <= 1;
+	   end // else: !if(writeable[write_sel]==(NUM_BUFS-1))
+       else if(read_done)
+	 full <= 0;
+
+   always @(posedge clk)
+     if(reset | clear)
+       read_sel <= 0;
+     else
+       if(read_done)
+	 if(readable[read_sel]==(NUM_BUFS-1))
+	   read_sel <= 0;
+	 else
+	   read_sel <= read_sel + 1;
+          
+   assign write_ready = writeable[write_sel];
+   assign read_ready = readable[read_sel];
+
+endmodule // dbsm
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 88f6809f8..91d02bfec 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -1,4 +1,3 @@
-`timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
 module gpmc
@@ -6,6 +5,9 @@ module gpmc
    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
 
+   // GPIOs for FIFO signalling
+   output rx_have_data, output tx_have_space,
+   
    // Wishbone signals
    input wb_clk, input wb_rst,
    output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
@@ -13,8 +15,8 @@ module gpmc
 
    // RAM Interface signals
    input ram_clk, 
-   input read_en, input read_sel, input [8:0] read_addr, output [31:0] read_data, output read_rdy,
-   input write_en, input write_sel, input [8:0] write_addr, input [31:0] write_data, output write_rdy
+   input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done,
+   input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done
    );
 
    wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
@@ -25,14 +27,35 @@ module gpmc
 
    // CS4 is RAM_2PORT for high-speed data
    // Writes go into one RAM, reads come from the other
+
+
+   // ////////////////////////////////////////////
+   // Write path
+   wire 	read_sel_in, write_sel_in, clear_in;
+   wire 	write_done_in = ~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF);
+   
+   ram_2port_mixed_width buffer_in
+     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(),
+      .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel_in,read_addr}), .di32(0), .do32(read_data));
+
+   dbsm dbsm_in(.clk(wb_clk), .reset(wb_rst), .clear(clear_in),
+		.read_sel(read_sel_in), .read_ready(read_ready), .read_done(read_done),
+		.write_sel(write_sel_in), .write_ready(tx_have_space), .write_done(write_done_in));
+
+   
+   
+   // ////////////////////////////////////////////
+   // Read path
+   wire 	read_sel_out, write_sel_out, clear_out;
+   wire 	read_done_out = ~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF);
    
-   ram_2port_mixed_width buffer_from_host
-     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({store_pg,EM_A}), .di16(EM_D), .do16(),
-      .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel,read_addr}), .di32(0), .do32(read_data));
+   ram_2port_mixed_width buffer_out
+     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram),
+      .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_out,write_addr}), .di32(write_data), .do32());
 
-   ram_2port_mixed_width buffer_to_host
-     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({retr_page,EM_A}), .di16(0), .do16(EM_D_ram),
-      .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel,write_addr}), .di32(write_data), .do32());
+   dbsm dbsm_out(.clk(wb_clk), .reset(wb_rst), .clear(clear_out),
+		 .read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out),
+		 .write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done));
 
    // CS6 is Control, Wishbone bus bridge (wb master)
    // Sync version
@@ -67,13 +90,13 @@ module gpmc
    assign wb_cyc_o = wb_stb_o;
 
    always @(posedge wb_clk)
-     if( ~cs_del[0] & (we_del == 2'b10) )
+     if(~cs_del[0] & (we_del == 2'b10) )
        wb_we_o <= 1;
      else if(wb_ack_i)  // Turn off we when done.  Could also use we_del[0], others...
        wb_we_o <= 0;
 
    always @(posedge wb_clk)
-     if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
+     if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
        wb_stb_o <= 1;
      else if(wb_ack_i)
        wb_stb_o <= 0;
diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
index 38dde1fa5..1e7dcdde5 100644
--- a/usrp2/models/gpmc_model.v
+++ b/usrp2/models/gpmc_model.v
@@ -22,6 +22,7 @@ module gpmc_model
      end
    
    task GPMC_Write;
+      input ctrl;
       input [10:0] addr;
       input [15:0] data;
       begin
@@ -29,10 +30,14 @@ module gpmc_model
 	 EM_A <= addr[10:1];
 	 EM_D_int <= data;
 	 #2.01;
-	 EM_NCS6 <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
 	 #14;
 	 EM_NWE <= 0;
 	 #77.5;
+	 EM_NCS4 <= 1;
 	 EM_NCS6 <= 1;
 	 //#1.5;
 	 EM_NWE <= 1;
@@ -43,15 +48,20 @@ module gpmc_model
    endtask // GPMC_Write
 
    task GPMC_Read;
+      input ctrl;
       input [10:0] addr;
       begin
 	 #1.3;
 	 EM_A <= addr[10:1];
 	 #3;
-	 EM_NCS6 <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
 	 #14;
 	 EM_NOE <= 0;
 	 #77.5;
+	 EM_NCS4 <= 1;
 	 EM_NCS6 <= 1;
 	 //#1.5;
 	 $display("Data Read from GPMC: %X",EM_D);
@@ -64,9 +74,14 @@ module gpmc_model
    initial
      begin
 	#1000;
-	GPMC_Write(36,16'hBEEF);
+	GPMC_Write(1,36,16'hF00D);
 	#1000;
-	GPMC_Read(36);
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'hF00D);
+	GPMC_Write(0,38,16'hF00D);
+	GPMC_Write(0,40,16'hF00D);
+	GPMC_Write(0,11'h7FFE,16'hF00D);
 	#1000;
 	$finish;
      end
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 319645af6..3cae74c8a 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ps / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
 module tb_u1e();
@@ -20,10 +20,15 @@ module tb_u1e();
    wire [10:1] EM_A;
    wire [1:0]  EM_NBE;
    
-   reg  clk_fpga = 0;
+   reg  clk_fpga = 0, rst_fpga = 1;
    always #15.625 clk_fpga = ~clk_fpga;
+
+   initial #200
+     @(posedge clk_fpga)
+       rst_fpga <= 0;
    
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), 
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 667372434..066d02ca4 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -21,7 +21,8 @@ module u1e
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]),
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 12c566b6c..7feafeda8 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,8 +1,7 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
 
 module u1e_core
-  (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+  (input clk_fpga, input rst_fpga,
+   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd,
    
    // GPMC
@@ -14,7 +13,8 @@ module u1e_core
    inout [15:0] io_tx, inout [15:0] io_rx
    );
    
-   wire   wb_clk, wb_rst;
+   wire 	wb_clk = clk_fpga;
+   wire 	wb_rst = rst_fpga;
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // GPMC Slave to Wishbone Master
@@ -31,10 +31,18 @@ module u1e_core
 	      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
 	      .EM_NOE(EM_NOE),
 
+	      .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+	      
 	      .wb_clk(wb_clk), .wb_rst(wb_rst),
 	      .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
 	      .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	      .wb_ack_i(m0_ack));
+	      .wb_ack_i(m0_ack),
+
+	      .ram_clk(wb_clk),
+	      .read_en(read_en), .read_addr(read_addr), .read_data(read_data), 
+	      .read_ready(read_ready), .read_done(read_done),
+	      .write_en(write_en), .write_addr(write_addr), .write_data(write_data), 
+	      .write_ready(write_ready), .write_done(write_done) );
 
    assign wb_clk = clk_fpga;
 
@@ -130,7 +138,7 @@ module u1e_core
 			16'hBEEF;
    assign s0_ack = s0_stb & s0_cyc;
 
-   assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios;
+   assign { rx_overrun, tx_underrun } = reg_gpios;
 
    // /////////////////////////////////////////////////////////////////////////////////////
    // Slave 1, UART
-- 
cgit v1.2.3


From c8e869b2e685cb8a5c012498b7f47aaadf39698a Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 25 Feb 2010 18:38:48 -0800
Subject: loopback and test

---
 usrp2/models/gpmc_model.v | 11 ++++++-----
 usrp2/top/u1e/u1e_core.v  | 34 ++++++++++++++++++++++++++++++++--
 2 files changed, 38 insertions(+), 7 deletions(-)

(limited to 'usrp2/models')

diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
index 1e7dcdde5..3424671bd 100644
--- a/usrp2/models/gpmc_model.v
+++ b/usrp2/models/gpmc_model.v
@@ -78,11 +78,12 @@ module gpmc_model
 	#1000;
 	GPMC_Read(1,36);
 	#1000;
-	GPMC_Write(0,36,16'hF00D);
-	GPMC_Write(0,38,16'hF00D);
-	GPMC_Write(0,40,16'hF00D);
-	GPMC_Write(0,11'h7FFE,16'hF00D);
-	#1000;
+	GPMC_Write(0,36,16'h1234);
+	GPMC_Write(0,38,16'h5678);
+	GPMC_Write(0,40,16'h9abc);
+	GPMC_Write(0,11'h2F4,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hF00D);
+	#100000;
 	$finish;
      end
    
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 7feafeda8..e14152f33 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -26,6 +26,13 @@ module u1e_core
    wire [aw-1:0] m0_adr;
    wire [sw-1:0] m0_sel;
    wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
+
+   // FIFO buffers
+   wire [31:0] 	 read_data, write_data;
+   wire [8:0] 	 read_addr, write_addr;
+   reg [8:0] 	 addr;
+   
+   wire 	 read_done, write_done, read_en, write_en, read_ready, write_ready;
    
    gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 	      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
@@ -43,9 +50,32 @@ module u1e_core
 	      .read_ready(read_ready), .read_done(read_done),
 	      .write_en(write_en), .write_addr(write_addr), .write_data(write_data), 
 	      .write_ready(write_ready), .write_done(write_done) );
+   
+   // Loopback
+   assign write_data = read_data;
+   
+   reg [10:0] 	 counter;
+   assign write_addr = counter[10:2];
+   assign read_addr = counter[10:2];   
 
-   assign wb_clk = clk_fpga;
-
+   assign read_done = (counter == 11'h7FF);
+   assign write_done = (counter == 11'h7FF);
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       counter <= 0;
+     else 
+       if(counter == 0)
+	 counter <= write_ready & read_ready;
+       else if(counter == 11'h7FF)
+	 counter <= 0;
+       else
+	 counter <= counter + 1;
+   
+   assign read_en = (counter[1:0] == 1);
+   assign write_en = (counter[1:0] == 2);
+   
+	      
    // /////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Intercon, single master
    wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
-- 
cgit v1.2.3


From f95bf4d8d94511d26a5bb1f52823f8ffd5f637fe Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 12 Apr 2010 19:20:22 -0700
Subject: lengthened delay between cycles, added more transactions on the data
 bus

---
 usrp2/models/gpmc_model.v | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

(limited to 'usrp2/models')

diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
index 3424671bd..6066ede6e 100644
--- a/usrp2/models/gpmc_model.v
+++ b/usrp2/models/gpmc_model.v
@@ -41,7 +41,7 @@ module gpmc_model
 	 EM_NCS6 <= 1;
 	 //#1.5;
 	 EM_NWE <= 1;
-	 #6;
+	 #60;
 	 EM_A <= 10'bz;
 	 EM_D_int <= 16'bz;
       end
@@ -82,7 +82,12 @@ module gpmc_model
 	GPMC_Write(0,38,16'h5678);
 	GPMC_Write(0,40,16'h9abc);
 	GPMC_Write(0,11'h2F4,16'hF00D);
-	GPMC_Write(0,11'h7FE,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
 	#100000;
 	$finish;
      end
-- 
cgit v1.2.3


From d7342b46abac60bf4e2811ac4798dc4e06b5844f Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 15 Apr 2010 14:51:41 -0700
Subject: synchronous and asynchronous gpmc models

---
 usrp2/models/gpmc_model.v       | 95 ----------------------------------------
 usrp2/models/gpmc_model_async.v | 95 ++++++++++++++++++++++++++++++++++++++++
 usrp2/models/gpmc_model_sync.v  | 97 +++++++++++++++++++++++++++++++++++++++++
 usrp2/top/u1e/tb_u1e.v          |  2 +-
 4 files changed, 193 insertions(+), 96 deletions(-)
 delete mode 100644 usrp2/models/gpmc_model.v
 create mode 100644 usrp2/models/gpmc_model_async.v
 create mode 100644 usrp2/models/gpmc_model_sync.v

(limited to 'usrp2/models')

diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
deleted file mode 100644
index 6066ede6e..000000000
--- a/usrp2/models/gpmc_model.v
+++ /dev/null
@@ -1,95 +0,0 @@
-
-
-module gpmc_model
-  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
-   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
-   output reg EM_NWE, output reg EM_NOE );
-
-   assign EM_CLK = 0;
-   reg [15:0] EM_D_int;
-   assign EM_D = EM_D_int;
-   
-   initial
-     begin
-	EM_A <= 10'bz;
-	EM_NBE <= 2'b11;
-	EM_NWE <= 1;
-	EM_NOE <= 1;
-	EM_NCS4 <= 1;
-	EM_NCS6 <= 1;
-	EM_D_int <= 16'bz;
- 	EM_WAIT0 <= 0;  // FIXME this is actually an input
-     end
-   
-   task GPMC_Write;
-      input ctrl;
-      input [10:0] addr;
-      input [15:0] data;
-      begin
-	 #2.3;
-	 EM_A <= addr[10:1];
-	 EM_D_int <= data;
-	 #2.01;
-	 if(ctrl)
-	   EM_NCS6 <= 0;
-	 else
-	   EM_NCS4 <= 0;
-	 #14;
-	 EM_NWE <= 0;
-	 #77.5;
-	 EM_NCS4 <= 1;
-	 EM_NCS6 <= 1;
-	 //#1.5;
-	 EM_NWE <= 1;
-	 #60;
-	 EM_A <= 10'bz;
-	 EM_D_int <= 16'bz;
-      end
-   endtask // GPMC_Write
-
-   task GPMC_Read;
-      input ctrl;
-      input [10:0] addr;
-      begin
-	 #1.3;
-	 EM_A <= addr[10:1];
-	 #3;
-	 if(ctrl)
-	   EM_NCS6 <= 0;
-	 else
-	   EM_NCS4 <= 0;
-	 #14;
-	 EM_NOE <= 0;
-	 #77.5;
-	 EM_NCS4 <= 1;
-	 EM_NCS6 <= 1;
-	 //#1.5;
-	 $display("Data Read from GPMC: %X",EM_D);
-	 EM_NOE <= 1;
-	 #254;
-	 EM_A <= 10'bz;
-      end
-   endtask // GPMC_Read
-   
-   initial
-     begin
-	#1000;
-	GPMC_Write(1,36,16'hF00D);
-	#1000;
-	GPMC_Read(1,36);
-	#1000;
-	GPMC_Write(0,36,16'h1234);
-	GPMC_Write(0,38,16'h5678);
-	GPMC_Write(0,40,16'h9abc);
-	GPMC_Write(0,11'h2F4,16'hF00D);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	#100000;
-	$finish;
-     end
-   
-endmodule // gpmc_model
diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v
new file mode 100644
index 000000000..a63a5a8fd
--- /dev/null
+++ b/usrp2/models/gpmc_model_async.v
@@ -0,0 +1,95 @@
+
+
+module gpmc_model_async
+  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   assign EM_CLK = 0;
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+   
+   initial
+     begin
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 #2.3;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #2.01;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NWE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 EM_NWE <= 1;
+	 #60;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #1.3;
+	 EM_A <= addr[10:1];
+	 #3;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NOE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000;
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'h1234);
+	GPMC_Write(0,38,16'h5678);
+	GPMC_Write(0,40,16'h9abc);
+	GPMC_Write(0,11'h2F4,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	#100000;
+	$finish;
+     end
+   
+endmodule // gpmc_model_async
diff --git a/usrp2/models/gpmc_model_sync.v b/usrp2/models/gpmc_model_sync.v
new file mode 100644
index 000000000..641720c15
--- /dev/null
+++ b/usrp2/models/gpmc_model_sync.v
@@ -0,0 +1,97 @@
+
+
+module gpmc_model_sync
+  (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+
+   initial
+     begin
+	EM_CLK <= 0;
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #10;
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 1;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+	 #100;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #1.3;
+	 EM_A <= addr[10:1];
+	 #3;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NOE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000;
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'h1234);
+	GPMC_Write(0,38,16'h5678);
+	GPMC_Write(0,40,16'h9abc);
+	GPMC_Write(0,11'h2F4,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	#100000;
+	$finish;
+     end
+   
+endmodule // gpmc_model
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 3cae74c8a..31e4fcb69 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -33,7 +33,7 @@ module tb_u1e();
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
 
-   gpmc_model gpmc_model
+   gpmc_model_async gpmc_model_async
      (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
       .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
       .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
-- 
cgit v1.2.3


From 2e6079841b7509f08a54c67db2ec19e07329e0d9 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 15 Apr 2010 16:14:57 -0700
Subject: change time parameters because Xilinx IP has a 1ps timescale

---
 usrp2/models/gpmc_model_async.v | 41 +++++++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 14 deletions(-)

(limited to 'usrp2/models')

diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v
index a63a5a8fd..64b596284 100644
--- a/usrp2/models/gpmc_model_async.v
+++ b/usrp2/models/gpmc_model_async.v
@@ -1,4 +1,4 @@
-
+`timescale 1ps/1ps
 
 module gpmc_model_async
   (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
@@ -26,22 +26,22 @@ module gpmc_model_async
       input [10:0] addr;
       input [15:0] data;
       begin
-	 #2.3;
+	 #23000;
 	 EM_A <= addr[10:1];
 	 EM_D_int <= data;
-	 #2.01;
+	 #20100;
 	 if(ctrl)
 	   EM_NCS6 <= 0;
 	 else
 	   EM_NCS4 <= 0;
-	 #14;
+	 #14000;
 	 EM_NWE <= 0;
-	 #77.5;
+	 #77500;
 	 EM_NCS4 <= 1;
 	 EM_NCS6 <= 1;
 	 //#1.5;
 	 EM_NWE <= 1;
-	 #60;
+	 #60000;
 	 EM_A <= 10'bz;
 	 EM_D_int <= 16'bz;
       end
@@ -51,33 +51,33 @@ module gpmc_model_async
       input ctrl;
       input [10:0] addr;
       begin
-	 #1.3;
+	 #13000;
 	 EM_A <= addr[10:1];
-	 #3;
+	 #3000;
 	 if(ctrl)
 	   EM_NCS6 <= 0;
 	 else
 	   EM_NCS4 <= 0;
-	 #14;
+	 #14000;
 	 EM_NOE <= 0;
-	 #77.5;
+	 #77500;
 	 EM_NCS4 <= 1;
 	 EM_NCS6 <= 1;
 	 //#1.5;
 	 $display("Data Read from GPMC: %X",EM_D);
 	 EM_NOE <= 1;
-	 #254;
+	 #254000;
 	 EM_A <= 10'bz;
       end
    endtask // GPMC_Read
    
    initial
      begin
-	#1000;
+	#1000000;
 	GPMC_Write(1,36,16'hF00D);
-	#1000;
+	#1000000;
 	GPMC_Read(1,36);
-	#1000;
+	#1000000;
 	GPMC_Write(0,36,16'h1234);
 	GPMC_Write(0,38,16'h5678);
 	GPMC_Write(0,40,16'h9abc);
@@ -89,6 +89,19 @@ module gpmc_model_async
 	GPMC_Write(0,11'h7FE,16'hDEAD);
 	GPMC_Write(0,11'h7FE,16'hDEAD);
 	#100000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	#100000;
+	GPMC_Read(0,0);
+	#100000000;
 	$finish;
      end
    
-- 
cgit v1.2.3


From beccd823da07b7c8b8d95b4688c6e05732f66165 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 15 Apr 2010 17:55:22 -0700
Subject: async seems to work with packet lengths now.  Still need to do
 wishbone regs for gpmc

---
 usrp2/gpmc/fifo_to_gpmc_async.v |  9 +-------
 usrp2/gpmc/fifo_watcher.v       | 38 +++++++++++++++++++++++++++-------
 usrp2/gpmc/gpmc_async.v         | 10 ++++-----
 usrp2/models/gpmc_model_async.v | 46 ++++++++++++++++++++++++++++++-----------
 usrp2/top/u1e/Makefile          |  6 +++---
 5 files changed, 72 insertions(+), 37 deletions(-)

(limited to 'usrp2/models')

diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v
index 4f253e1b5..5ac8b19bd 100644
--- a/usrp2/gpmc/fifo_to_gpmc_async.v
+++ b/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -8,7 +8,7 @@ module fifo_to_gpmc_async
   (input clk, input reset, input clear,
    input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
    output [15:0] EM_D, input EM_NCS, input EM_NOE,
-   input [15:0] frame_len, output reg bus_error);
+   input [15:0] frame_len);
 
    // Synchronize the async control signals
    reg [1:0] 	cs_del, oe_del;
@@ -35,11 +35,4 @@ module fifo_to_gpmc_async
 
    assign dst_rdy_o = do_read;
 
-   always @(posedge clk)
-     if(reset)
-       bus_error <= 0;
-     else if(dst_rdy_o & ~src_rdy_i)
-       bus_error <= 1;
-   
-
 endmodule // fifo_to_gpmc_async
diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v
index 8b8f1abfb..da2051b04 100644
--- a/usrp2/gpmc/fifo_watcher.v
+++ b/usrp2/gpmc/fifo_watcher.v
@@ -2,25 +2,47 @@
 
 module fifo_watcher
   (input clk, input reset, input clear,
-   input src_rdy, input dst_rdy, input sof, input eof,
-   output have_packet, output [15:0] length, input next);
+   input src_rdy1, input dst_rdy1, input sof1, input eof1,
+   input src_rdy2, input dst_rdy2, input sof2, input eof2,
+   output have_packet, output [15:0] length, output reg bus_error);
 
-   wire   write = src_rdy & dst_rdy & eof;
+   wire   write = src_rdy1 & dst_rdy1 & eof1;
+   wire   read = src_rdy2 & dst_rdy2 & eof2;
+   wire   have_packet_int;
+   reg [15:0] counter;
    
    fifo_short #(.WIDTH(16)) frame_lengths
      (.clk(clk), .reset(reset), .clear(clear),
       .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
-      .dataout(length), .src_rdy_o(have_packet), .dst_rdy_i(next) );
+      .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read) );
 
-   reg [15:0] counter;
    always @(posedge clk)
      if(reset | clear)
        counter <= 1;   // Start at 1
-     else if(src_rdy & dst_rdy)
-       if(eof)
+     else if(src_rdy1 & dst_rdy1)
+       if(eof1)
 	 counter <= 1;
        else
 	 counter <= counter + 1;
-   
 
+   always @(posedge clk)
+     if(reset | clear)
+       bus_error <= 0;
+     else if(dst_rdy2 & ~src_rdy2)
+       bus_error <= 1;
+     else if(read & ~have_packet_int)
+       bus_error <= 1;
+
+   reg 	      in_packet;
+   assign have_packet = have_packet_int & ~in_packet;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       in_packet <= 0;
+     else if(src_rdy2 & dst_rdy2)
+       if(eof2)
+	 in_packet <= 0;
+       else
+	 in_packet <= 1;
+   
 endmodule // fifo_watcher
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index c4cf0ef89..22e56cc89 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -67,7 +67,6 @@ module gpmc_async
    wire [17:0] 	rx18_data, rx18b_data;
    wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
    wire [15:0] 	rx_fifo_space, rx_frame_len;
-   assign rx_frame_len = tx_frame_len;
    
    fifo36_to_fifo18 f18_to_f36
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
@@ -83,15 +82,14 @@ module gpmc_async
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
       .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
-      .frame_len(rx_frame_len), .bus_error(bus_error_rx) );
+      .frame_len(rx_frame_len) );
 
    fifo_watcher fifo_watcher
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]),
-      .have_packet(), .length(), .next() );
+      .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]),
+      .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]),
+      .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) );
 
-   assign rx_have_data = 0;
-   
    // ////////////////////////////////////////////
    // Control path on CS6
    
diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v
index 64b596284..beeaee028 100644
--- a/usrp2/models/gpmc_model_async.v
+++ b/usrp2/models/gpmc_model_async.v
@@ -78,28 +78,50 @@ module gpmc_model_async
 	#1000000;
 	GPMC_Read(1,36);
 	#1000000;
-	GPMC_Write(0,36,16'h1234);
-	GPMC_Write(0,38,16'h5678);
-	GPMC_Write(0,40,16'h9abc);
-	GPMC_Write(0,11'h2F4,16'hF00D);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	#100000;
+	GPMC_Write(0,0,16'h1234);
+	GPMC_Write(0,0,16'h5678);
+	GPMC_Write(0,0,16'h9abc);
+	GPMC_Write(0,0,16'hF00D);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	#1000000;
+	GPMC_Write(0,0,16'h1234);
+	GPMC_Write(0,0,16'h5678);
+	GPMC_Write(0,0,16'h9abc);
+	GPMC_Write(0,0,16'hF00D);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'h9876);
+	#1000000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
+	#1000000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
 	GPMC_Read(0,0);
-	#100000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	#1000000;
 	GPMC_Read(0,0);
 	#100000000;
 	$finish;
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index 160e67894..e15a49e10 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -176,12 +176,12 @@ timing/time_receiver.v \
 timing/time_sender.v \
 timing/time_sync.v \
 timing/timer.v \
-gpmc/gpmc.v \
+gpmc/gpmc_async.v \
 gpmc/edge_sync.v \
 gpmc/dbsm.v \
 gpmc/gpmc_to_fifo_async.v \
-gpmc/gpmc_to_fifo_sync.v \
-gpmc/fifo_to_gpmc_sync.v \
+gpmc/fifo_to_gpmc_async.v \
+gpmc/fifo_watcher.v \
 gpmc/gpmc_wb.v \
 top/u1e/u1e_core.v \
 top/u1e/u1e.ucf \
-- 
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