From 57f956af2f9cc3463970e8d47c2f59ec549accbf Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Feb 2011 17:04:30 -0800 Subject: e100: integrate loopback and timed testing into main image --- usrp2/gpmc/gpmc_async.v | 94 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 89 insertions(+), 5 deletions(-) (limited to 'usrp2/gpmc') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 23bad56ae..b2c91dfbc 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -1,7 +1,9 @@ ////////////////////////////////////////////////////////////////////////////////// module gpmc_async - #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + #(parameter TXFIFOSIZE = 11, + parameter RXFIFOSIZE = 11, + parameter BUSDEBUG = 1) (// GPMC signals input arst, input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -70,9 +72,9 @@ module gpmc_async .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), - .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)); // //////////////////////////////////////////// // RX Data Path @@ -85,8 +87,8 @@ module gpmc_async wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE @@ -126,5 +128,87 @@ module gpmc_async .wb_ack_i(wb_ack_i) ); assign debug = pkt_count; + + // //////////////////////////////////////////// + // Test support, traffic generator, loopback, etc. + + // RX side muxes test data into the same stream + wire [35:0] timedrx_data, loopbackrx_data, testrx_data, rx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data, tx_data; + wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy; + wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, + testtx_src_rdy, testtx_dst_rdy, tx_src_rdy, tx_dst_rdy; + wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; + + wire [31:0] total, crc_err, seq_err, len_err; + wire [7:0] rx_rate, tx_rate; + wire rx_enable, tx_enable; + wire underrun, overrun; + wire sel_testtx, sel_loopbacktx; + + fifo36_mux rx_test_mux_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy), + .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy), + .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy)); + + fifo36_mux rx_test_mux_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy), + .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + fifo_short #(.WIDTH(36)) loopback_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx), + .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy), + .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy)); + // Crossbar used as a demux for switching TX stream to main DSP or to test logic + crossbar36 tx_crossbar_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_testtx), + .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy), + .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i), + .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) ); + + crossbar36 tx_crossbar_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_loopbacktx), + .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy), + .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy), + .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) ); + + // Fixed rate TX traffic consumer + fifo_pacer tx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable), + .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), + .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), + .underrun(underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // Fixed rate RX traffic generator + packet_generator32 pktgen32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .header({len_err,seq_err,crc_err,total}), + .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable), + .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), + .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), + .underrun(), .overrun(overrun)); + + // FIXME -- hook up crossbar controls + // FIXME -- collect error stats + // FIXME -- set rates and enables on pacers + // FIXME -- make sure packet completes before we shutoff + // FIXME -- handle overrun and underrun + endmodule // gpmc_async -- cgit v1.2.3 From 74346c49eda60ed5916908efb8d245b7e8852f6f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Feb 2011 17:58:04 -0800 Subject: hook up under/overruns for debug purposes --- usrp2/gpmc/gpmc_async.v | 10 +++++----- usrp2/top/u1e/u1e_core.v | 10 +++++++--- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'usrp2/gpmc') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index b2c91dfbc..38bfd3e25 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -23,7 +23,8 @@ module gpmc_async input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, input [15:0] tx_frame_len, output [15:0] rx_frame_len, - + + output tx_underrun, output rx_overrun, output [31:0] debug ); @@ -144,7 +145,6 @@ module gpmc_async wire [31:0] total, crc_err, seq_err, len_err; wire [7:0] rx_rate, tx_rate; wire rx_enable, tx_enable; - wire underrun, overrun; wire sel_testtx, sel_loopbacktx; fifo36_mux rx_test_mux_lvl_1 @@ -186,7 +186,7 @@ module gpmc_async (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable), .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), - .underrun(underrun), .overrun()); + .underrun(tx_underrun), .overrun()); packet_verifier32 pktver32 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), @@ -203,10 +203,10 @@ module gpmc_async (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable), .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), - .underrun(), .overrun(overrun)); + .underrun(), .overrun(rx_overrun)); // FIXME -- hook up crossbar controls - // FIXME -- collect error stats + // // FIXME -- collect error stats // FIXME -- set rates and enables on pacers // FIXME -- make sure packet completes before we shutoff // FIXME -- handle overrun and underrun diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4f5a3e112..c0e92ec6c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -50,7 +50,10 @@ module u1e_core wire set_stb; wire [31:0] debug_vt; - + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(global_reset)); @@ -107,6 +110,7 @@ module u1e_core .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), .debug(debug_gpmc)); wire rx_sof = rx_data[32]; @@ -135,7 +139,7 @@ module u1e_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun), + .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -171,7 +175,7 @@ module u1e_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(underrun), .run(run_tx), + .underrun(tx_underrun_dsp), .run(run_tx), .debug(debug_vt)); assign tx_i = tx_i_int[15:2]; -- cgit v1.2.3 From 3660330fae97026a74cd5d396a04040ab324ca09 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Feb 2011 18:22:49 -0800 Subject: move declarations to before use --- usrp2/gpmc/gpmc_async.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'usrp2/gpmc') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 38bfd3e25..895b68a9f 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -52,8 +52,8 @@ module gpmc_async wire [17:0] tx18_data, tx18b_data; wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; wire [15:0] tx_fifo_space; - wire [35:0] tx36_data; - wire tx36_src_rdy, tx36_dst_rdy; + wire [35:0] tx36_data, tx_data; + wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy; gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), @@ -83,8 +83,8 @@ module gpmc_async wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; wire [15:0] rx_fifo_space; - wire [35:0] rx36_data; - wire rx36_src_rdy, rx36_dst_rdy; + wire [35:0] rx36_data, rx_data; + wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 @@ -134,12 +134,12 @@ module gpmc_async // Test support, traffic generator, loopback, etc. // RX side muxes test data into the same stream - wire [35:0] timedrx_data, loopbackrx_data, testrx_data, rx_data; - wire [35:0] timedtx_data, loopbacktx_data, testtx_data, tx_data; + wire [35:0] timedrx_data, loopbackrx_data, testrx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data; wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, - testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy; + testrx_src_rdy, testrx_dst_rdy; wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, - testtx_src_rdy, testtx_dst_rdy, tx_src_rdy, tx_dst_rdy; + testtx_src_rdy, testtx_dst_rdy; wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; wire [31:0] total, crc_err, seq_err, len_err; -- cgit v1.2.3 From ee50f438752a4beb780c3340026e2f29c1c32a3e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 17 Feb 2011 16:33:41 -0800 Subject: u1e: hook up tester controls --- usrp2/gpmc/gpmc_async.v | 12 +++++++----- usrp2/top/u1e/u1e_core.v | 10 ++++++---- 2 files changed, 13 insertions(+), 9 deletions(-) (limited to 'usrp2/gpmc') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 895b68a9f..7d38c66cb 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -25,6 +25,7 @@ module gpmc_async input [15:0] tx_frame_len, output [15:0] rx_frame_len, output tx_underrun, output rx_overrun, + input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug ); @@ -143,9 +144,10 @@ module gpmc_async wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; wire [31:0] total, crc_err, seq_err, len_err; - wire [7:0] rx_rate, tx_rate; - wire rx_enable, tx_enable; - wire sel_testtx, sel_loopbacktx; + wire sel_testtx = test_ctrl[0]; + wire sel_loopbacktx = test_ctrl[1]; + wire pkt_src_enable = test_ctrl[2]; + wire pkt_sink_enable = test_ctrl[3]; fifo36_mux rx_test_mux_lvl_1 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), @@ -183,7 +185,7 @@ module gpmc_async // Fixed rate TX traffic consumer fifo_pacer tx_pacer - (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable), + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable), .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), .underrun(tx_underrun), .overrun()); @@ -200,7 +202,7 @@ module gpmc_async .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); fifo_pacer rx_pacer - (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable), + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable), .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), .underrun(), .overrun(rx_overrun)); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index c0e92ec6c..174a2a3f8 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -44,6 +44,8 @@ module u1e_core wire pps_int; wire [63:0] vita_time, vita_time_pps; reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; wire [7:0] set_addr; wire [31:0] set_data; @@ -78,7 +80,6 @@ module u1e_core tx_err_src_rdy, tx_err_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; - wire [7:0] rate; wire bus_error; wire clear_tx, clear_rx; @@ -111,6 +112,8 @@ module u1e_core .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .test_rate(test_rate), .test_ctrl(test_ctrl), .debug(debug_gpmc)); wire rx_sof = rx_data[32]; @@ -285,9 +288,8 @@ module u1e_core xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) - assign tx_enable = xfer_rate[15]; - assign rx_enable = xfer_rate[14]; - assign rate = xfer_rate[7:0]; + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; -- cgit v1.2.3 From 87f8f6fca6742a4263b636aa5632f228fccd18f2 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 25 Feb 2011 13:46:03 -0500 Subject: timed tester : Bring out src/dst flags for rx chain for testing. --- usrp2/gpmc/gpmc_async.v | 12 +++++++++++- usrp2/top/u1e/u1e_core.v | 4 ++++ 2 files changed, 15 insertions(+), 1 deletion(-) (limited to 'usrp2/gpmc') diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 7d38c66cb..053df5b18 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -129,7 +129,7 @@ module gpmc_async .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i) ); - assign debug = pkt_count; +// assign debug = pkt_count; // //////////////////////////////////////////// // Test support, traffic generator, loopback, etc. @@ -213,4 +213,14 @@ module gpmc_async // FIXME -- make sure packet completes before we shutoff // FIXME -- handle overrun and underrun +wire [0:17] dummy18; + +assign debug = {dummy18, timedrx_src_rdy_int, timedrx_dst_rdy_int, + timedrx_src_rdy, timedrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy, + rx_src_rdy, rx_dst_rdy, + rx36_src_rdy, rx36_dst_rdy, + rx18_src_rdy, rx18_dst_rdy, + rx18b_src_rdy, rx18b_dst_rdy}; + endmodule // gpmc_async diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 174a2a3f8..a5a477202 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -408,10 +408,14 @@ module u1e_core assign debug_clk = { EM_CLK, clk_fpga }; +/* assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; +*/ + assign debug = debug_gpmc; + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; -- cgit v1.2.3 From 98a1a03de054306f57be68e1b498c1d39a954472 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Feb 2011 15:17:31 -0800 Subject: fifo36_mux now has shortfifos on the input ports as well as output --- usrp2/fifo/fifo36_mux.v | 37 +++++++++++++++++++++++++------------ usrp2/gpmc/fifo_to_gpmc_async.v | 5 ----- usrp2/gpmc/gpmc_async.v | 4 +++- 3 files changed, 28 insertions(+), 18 deletions(-) (limited to 'usrp2/gpmc') diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index c6fd40f27..fa4243efe 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -10,6 +10,19 @@ module fifo36_mux input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + wire [35:0] data0_int, data1_int; + wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int; + + fifo_short #(.WIDTH(36)) mux_fifo_in0 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_i), + .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int)); + + fifo_short #(.WIDTH(36)) mux_fifo_in1 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_i), + .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int)); + localparam MUX_IDLE0 = 0; localparam MUX_DATA0 = 1; localparam MUX_IDLE1 = 2; @@ -17,8 +30,8 @@ module fifo36_mux reg [1:0] state; - wire eof0 = data0_i[33]; - wire eof1 = data1_i[33]; + wire eof0 = data0_int[33]; + wire eof1 = data1_int[33]; wire [35:0] data_int; wire src_rdy_int, dst_rdy_int; @@ -29,33 +42,33 @@ module fifo36_mux else case(state) MUX_IDLE0 : - if(src0_rdy_i) + if(src0_rdy_int) state <= MUX_DATA0; - else if(src1_rdy_i) + else if(src1_rdy_int) state <= MUX_DATA1; MUX_DATA0 : - if(src0_rdy_i & dst_rdy_int & eof0) + if(src0_rdy_int & dst_rdy_int & eof0) state <= prio ? MUX_IDLE0 : MUX_IDLE1; MUX_IDLE1 : - if(src1_rdy_i) + if(src1_rdy_int) state <= MUX_DATA1; - else if(src0_rdy_i) + else if(src0_rdy_int) state <= MUX_DATA0; MUX_DATA1 : - if(src1_rdy_i & dst_rdy_int & eof1) + if(src1_rdy_int & dst_rdy_int & eof1) state <= MUX_IDLE0; default : state <= MUX_IDLE0; endcase // case (state) - assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0; - assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0; - assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_int = (state==MUX_DATA0) ? data0_i : data1_i; + assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0; + assign data_int = (state==MUX_DATA0) ? data0_int : data1_int; fifo_short #(.WIDTH(36)) mux_fifo (.clk(clk), .reset(reset), .clear(clear), diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index cf8b6e861..9a8e37ce9 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -1,9 +1,4 @@ -// Assumes an asynchronous GPMC cycle -// If a packet bigger or smaller than we are told is sent, behavior is undefined. -// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. -// If there is a bus error, we should be reset - module fifo_to_gpmc_async (input clk, input reset, input clear, input [17:0] data_i, input src_rdy_i, output dst_rdy_o, diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 053df5b18..02bf45b8a 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -215,7 +215,9 @@ module gpmc_async wire [0:17] dummy18; -assign debug = {dummy18, timedrx_src_rdy_int, timedrx_dst_rdy_int, +assign debug = {8'd0, + test_rate, + pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int, timedrx_src_rdy, timedrx_dst_rdy, testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy, -- cgit v1.2.3