From a4dc4a539a61d94a2d18b4576371d230c0dc6514 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 18 Mar 2011 16:11:02 -0700 Subject: u1p: use 18 bit fifos and use full size of a block ram in the tx path --- usrp2/gpif/gpif_wr.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'usrp2/gpif') diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index e9b3c72ea..bf95931dc 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -44,19 +44,20 @@ module gpif_wr else gpif_full_d <= fifo_space < 256; - wire [18:0] data_int; + wire [17:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo + fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo (.clk(gpif_clk), .reset(gpif_rst), .clear(0), - .datain({1'b0,eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); - fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) wr_fifo_2clk + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .rclk(sys_clk), .dataout(data_o[18:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); - + assign data_o[18] = 1'b0; + // Control Path wire [15:0] ctrl_fifo_space; always @(posedge gpif_clk) -- cgit v1.2.3