From 179c651716798bd7b3aaa74c6a546f041e2e3688 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 11 Dec 2010 17:44:27 -0800 Subject: packet_router: raise enable for bram reads the cycle before as well --- usrp2/fifo/dsp_framer36.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'usrp2/fifo/dsp_framer36.v') diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index fbdc9fbd7..e44f91305 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -29,6 +29,7 @@ module dsp_framer36 //The header is generated here from the count. wire [31:0] dsp_frm_data_bram; wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; + wire dsp_frm_enb = (dsp_frm_state == DSP_FRM_STATE_WRITE)? (out_ready & out_valid) : 1'b1; assign out_data = (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( @@ -44,7 +45,7 @@ module dsp_framer36 .ENA(inp_ready),.SSRA(0),.WEA(inp_ready), //port B = DSP framer interface (reads from BRAM) .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) + .ENB(dsp_frm_enb),.SSRB(0),.WEB(1'b0) ); always @(posedge clk) -- cgit v1.2.3 From 04f391a2948c07ff1fed9f02497c85cf0f098fee Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Dec 2010 01:09:29 -0800 Subject: packet_router: reverted enable change to dsp framer, it was already correct --- usrp2/fifo/dsp_framer36.v | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'usrp2/fifo/dsp_framer36.v') diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index e44f91305..fbdc9fbd7 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -29,7 +29,6 @@ module dsp_framer36 //The header is generated here from the count. wire [31:0] dsp_frm_data_bram; wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; - wire dsp_frm_enb = (dsp_frm_state == DSP_FRM_STATE_WRITE)? (out_ready & out_valid) : 1'b1; assign out_data = (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( @@ -45,7 +44,7 @@ module dsp_framer36 .ENA(inp_ready),.SSRA(0),.WEA(inp_ready), //port B = DSP framer interface (reads from BRAM) .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), - .ENB(dsp_frm_enb),.SSRB(0),.WEB(1'b0) + .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) ); always @(posedge clk) -- cgit v1.2.3 From 6c1d4ebdbd2229654976dd672a5433c300dc0d17 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 12 Dec 2010 17:48:58 -0800 Subject: packet_router: harmless logic tweaks --- usrp2/fifo/dsp_framer36.v | 10 +++++----- usrp2/fifo/packet_router.v | 9 +++------ 2 files changed, 8 insertions(+), 11 deletions(-) (limited to 'usrp2/fifo/dsp_framer36.v') diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index fbdc9fbd7..34a05d91e 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -20,10 +20,10 @@ module dsp_framer36 wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1; //DSP input stream ready in the following states - assign inp_ready = - (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : ( - (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : ( - 1'b0)); + assign inp_ready = ( + dsp_frm_state == DSP_FRM_STATE_WAIT_SOF || + dsp_frm_state == DSP_FRM_STATE_WAIT_EOF + )? 1'b1 : 1'b0; //DSP framer output data mux (header or BRAM): //The header is generated here from the count. @@ -41,7 +41,7 @@ module dsp_framer36 RAMB16_S36_S36 dsp_frm_buff( //port A = DSP input interface (writes to BRAM) .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0), - .ENA(inp_ready),.SSRA(0),.WEA(inp_ready), + .ENA(inp_ready & inp_valid),.SSRA(0),.WEA(inp_ready & inp_valid), //port B = DSP framer interface (reads from BRAM) .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 5118c69b3..9491d4346 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -253,13 +253,10 @@ module packet_router assign cpu_out_line_count = cpu_out_addr; wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1; - wire cpu_out_reading = ( + assign cpu_out_ready = ( cpu_out_state == CPU_OUT_STATE_WAIT_SOF || cpu_out_state == CPU_OUT_STATE_WAIT_EOF )? 1'b1 : 1'b0; - - wire cpu_out_we = cpu_out_reading; - assign cpu_out_ready = cpu_out_reading; assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; RAMB16_S36_S36 cpu_out_buff( @@ -267,8 +264,8 @@ module packet_router .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0), .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i), //port B = packet router interface to CPU (input only) - .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data),.DIPB(4'h0), - .ENB(cpu_out_we),.SSRB(0),.WEB(cpu_out_we) + .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data[31:0]),.DIPB(4'h0), + .ENB(cpu_out_ready & cpu_out_valid),.SSRB(0),.WEB(cpu_out_ready & cpu_out_valid) ); always @(posedge stream_clk) -- cgit v1.2.3