From 8cd377d7195fae6b5dcd04318c992231fa633999 Mon Sep 17 00:00:00 2001 From: ianb Date: Wed, 25 Aug 2010 16:32:43 -0700 Subject: Corrected extfifo code so that all registers that are on SRAM signals are packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly --- usrp2/extramfifo/nobl_fifo.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2/extramfifo/nobl_fifo.v') diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v index 62229e6c2..4c009d980 100644 --- a/usrp2/extramfifo/nobl_fifo.v +++ b/usrp2/extramfifo/nobl_fifo.v @@ -47,7 +47,7 @@ module nobl_fifo capacity <= (1 << FIFO_DEPTH) - 1; wr_pointer <= 0; rd_pointer <= 0; - space_avail <= 0; + space_avail <= 1; data_avail_int <= 0; end else @@ -56,7 +56,7 @@ module nobl_fifo // Capacity is already zero; Capacity is 1 and write is asserted (lookahead); both read and write are asserted (collision) space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) ); // Capacity has 1 cycle delay so look ahead here for corner case of read of last item in FIFO. - data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && read) ); + data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1)) || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read)) ); wr_pointer <= wr_pointer + write; rd_pointer <= rd_pointer + (~write && read); capacity <= capacity - write + (~write && read) ; -- cgit v1.2.3