From fb73ea172526319803756b985dd3c104881304b1 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 29 Jul 2010 21:25:26 -0700 Subject: Checkpoint checkin. Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet. --- usrp2/extramfifo/ext_fifo_tb.cmd | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 usrp2/extramfifo/ext_fifo_tb.cmd (limited to 'usrp2/extramfifo/ext_fifo_tb.cmd') diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd new file mode 100644 index 000000000..b0ab830dc --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.cmd @@ -0,0 +1,11 @@ +/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v +-y . +-y ../coregen/ +-y ../models +-y /home/ianb/usrp-fpga/usrp2/sdr_lib +-y /home/ianb/usrp-fpga/usrp2/control_lib +-y /home/ianb/usrp-fpga/usrp2/models +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src +-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib + -- cgit v1.2.3