From 6e0d78f4cbf6f0d6cda6007f11b4fb4dd4edaee9 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 12 Aug 2010 12:00:01 -0700 Subject: Found bug due to not accounting for the correct number of possible in flight READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus --- usrp2/extramfifo/ext_fifo.v | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'usrp2/extramfifo/ext_fifo.v') diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v index a506d71e2..c7e8f6cfb 100644 --- a/usrp2/extramfifo/ext_fifo.v +++ b/usrp2/extramfifo/ext_fifo.v @@ -57,10 +57,18 @@ module ext_fifo .dout(write_data), // Bus [17 : 0] .full(full1), .empty(empty1)); - assign dst_rdy_o = ~full1; + + assign dst_rdy_o = ~full1; + +/* -----\/----- EXCLUDED -----\/----- + assign space_avail = ~full2; + assign data_avail = ~empty1; + assign read_data = write_data; + -----/\----- EXCLUDED -----/\----- */ + // External FIFO running at ext clock rate and 18 bit width. - nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH)) + nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH),.FDEPTH(DEPTH)) nobl_fifo_i1 ( .clk(ext_clk), @@ -94,7 +102,8 @@ module ext_fifo .rd_en(dst_rdy_i), .dout(dataout), // Bus [35 : 0] .full(full2), - .almost_full(almost_full2), + .almost_full(), + .prog_full(almost_full2), .empty(empty2)); assign src_rdy_o = ~empty2; -- cgit v1.2.3