From 6d45600ada785cb50a01a17dcddf561d12501d22 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 10 Feb 2012 12:13:51 -0800 Subject: dsp rework: pass enables into glue, update power trig, parameterize, fix module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build --- usrp2/custom/custom_dsp_rx.v | 2 ++ usrp2/custom/custom_dsp_tx.v | 2 ++ usrp2/custom/power_trig.v | 83 ++++++++++++++++++++++++++------------------ 3 files changed, 53 insertions(+), 34 deletions(-) (limited to 'usrp2/custom') diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v index 2ceda7481..355adf008 100644 --- a/usrp2/custom/custom_dsp_rx.v +++ b/usrp2/custom/custom_dsp_rx.v @@ -55,6 +55,7 @@ module custom_dsp_rx //strobed samples {I16,Q16} from the RX DDC chain input [31:0] ddc_out_sample, input ddc_out_strobe, //high on valid sample + output ddc_out_enable, //enables DDC module //strobbed baseband samples {I16,Q16} from this module output [31:0] bb_sample, @@ -65,5 +66,6 @@ module custom_dsp_rx assign ddc_in_q = frontend_q; assign bb_sample = ddc_out_sample; assign bb_strobe = ddc_out_strobe; + assign ddc_out_enable = enable; endmodule //custom_dsp_rx diff --git a/usrp2/custom/custom_dsp_tx.v b/usrp2/custom/custom_dsp_tx.v index 5206a63a6..0848a187f 100644 --- a/usrp2/custom/custom_dsp_tx.v +++ b/usrp2/custom/custom_dsp_tx.v @@ -55,6 +55,7 @@ module custom_dsp_tx //strobed samples {I16,Q16} to the TX DUC chain output [31:0] duc_in_sample, input duc_in_strobe, //this is a backpressure signal + output duc_in_enable, //enables DUC module //strobbed baseband samples {I16,Q16} to this module input [31:0] bb_sample, @@ -65,5 +66,6 @@ module custom_dsp_tx assign frontend_q = duc_out_q; assign duc_in_sample = bb_sample; assign bb_strobe = duc_in_strobe; + assign duc_in_enable = enable; endmodule //custom_dsp_tx diff --git a/usrp2/custom/power_trig.v b/usrp2/custom/power_trig.v index ca213e901..b38059030 100644 --- a/usrp2/custom/power_trig.v +++ b/usrp2/custom/power_trig.v @@ -15,41 +15,56 @@ // along with this program. If not, see . // -//CUSTOMIZE ME! +// This a power trigger module implemented on top of the custom dsp template. +// Power triggering is implemented after the existing DDC chain. +// Triggering is controlled via user settings registers. -//The following module effects the IO of the DDC chain. -//By default, this entire module is a simple pass-through. - -//To implement DSP logic before the DDC: -//Implement custom DSP between frontend and ddc input. - -//To implement DSP logic after the DDC: -//Implement custom DSP between ddc output and baseband. - -//To bypass the DDC with custom logic: -//Implement custom DSP between frontend and baseband. +// Register 0: +// threshold for power trigger +// 32 bit unsigned fixed-point number of some arbitrary scaling module power_trig - #(parameter BASE=0) - (//control signals - input clk, input reset, input enable, - - // Setting Bus +#( + //frontend bus width + parameter WIDTH = 24, + parameter BASE = 0 +) +( + //control signals + input clock, //dsp clock + input reset, //active high synchronous reset + input clear, //active high on packet control init + input enable, //active high when streaming enabled + + //user settings bus, controlled through user setting regs API input set_stb, input [7:0] set_addr, input [31:0] set_data, - input run, - + //full rate inputs directly from the RX frontend + input [WIDTH-1:0] frontend_i, + input [WIDTH-1:0] frontend_q, + + //full rate outputs directly to the DDC chain + output [WIDTH-1:0] ddc_in_i, + output [WIDTH-1:0] ddc_in_q, + //strobed samples {I16,Q16} from the RX DDC chain input [31:0] ddc_out_sample, input ddc_out_strobe, //high on valid sample + output ddc_out_enable, //enables DDC module - //strobed baseband samples {I16,Q16} from this module + //strobbed baseband samples {I16,Q16} from this module output [31:0] bb_sample, - output bb_strobe, //high on valid sample + output bb_strobe //high on valid sample +); + + //leave frontend tied to existing ddc chain + assign ddc_in_i = frontend_i; + assign ddc_in_q = frontend_q; + + //ddc enable remains tied to global enable + assign ddc_out_enable = enable; - //debug output (optional) - output [31:0] debug - ); + //below we implement a power trigger between baseband samples and ddc output... reg [8:0] wr_addr; wire [8:0] rd_addr; @@ -69,23 +84,23 @@ module power_trig (.clka(clk),.ena(1),.wea(ddc_out_strobe),.addra(wr_addr),.dia(ddc_out_sample),.doa(), .clkb(clk),.enb(ddc_out_strobe),.web(1'b0),.addrb(rd_addr),.dib(32'hFFFF),.dob(delayed_sample)); - always @(posedge clk) - if(reset | ~run) + always @(posedge clock) + if(reset | ~enable) wr_addr <= 0; else if(ddc_out_strobe) wr_addr <= wr_addr + 1; - always @(posedge clk) - if(reset | ~run) + always @(posedge clock) + if(reset | ~enable) triggerable <= 0; else if(wr_addr == 9'h1FF) // Wait till we're nearly full triggerable <= 1; reg stb_d1, stb_d2; - always @(posedge clk) stb_d1 <= ddc_out_strobe; - always @(posedge clk) stb_d2 <= stb_d1; + always @(posedge clock) stb_d1 <= ddc_out_strobe; + always @(posedge clock) stb_d2 <= stb_d1; assign bb_sample = delayed_sample; assign bb_strobe = stb_d1 & triggered; @@ -96,16 +111,16 @@ module power_trig wire [35:0] prod; reg [31:0] sum; - MULT18X18S mult (.P(prod), .A(mult_in), .B(mult_in), .C(clk), .CE(ddc_out_strobe | stb_d1), .R(reset) ); + MULT18X18S mult (.P(prod), .A(mult_in), .B(mult_in), .C(clock), .CE(ddc_out_strobe | stb_d1), .R(reset) ); - always @(posedge clk) + always @(posedge clock) if(stb_d1) sum <= prod[35:4]; else if(stb_d2) sum <= sum + prod[35:4]; - always @(posedge clk) - if(reset | ~run | ~triggerable) + always @(posedge clock) + if(reset | ~enable | ~triggerable) triggered <= 0; else if(trigger) triggered <= 1; -- cgit v1.2.3