From 93185ca7719e8949e90b594676be6c3d2f709fb9 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 11 May 2010 15:48:47 -0700
Subject: allow settings bus to cross to a new clock domain, should help
 timing, but not attached yet

---
 usrp2/control_lib/settings_bus_crossclock.v | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 usrp2/control_lib/settings_bus_crossclock.v

(limited to 'usrp2/control_lib')

diff --git a/usrp2/control_lib/settings_bus_crossclock.v b/usrp2/control_lib/settings_bus_crossclock.v
new file mode 100644
index 000000000..b043aa0ad
--- /dev/null
+++ b/usrp2/control_lib/settings_bus_crossclock.v
@@ -0,0 +1,20 @@
+
+
+// This module takes the settings bus on one clock domain and crosses it over to another domain
+// Typically it will be used with the input settings bus on the wishbone clock, and either 
+// the system or dsp clock on the output side
+
+module settings_bus_crossclock
+  (input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
+   input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o);
+
+   wire  full, empty;
+   
+   fifo_xlnx_16x40_2clk settings_fifo
+     (.rst(rst_i),
+      .wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
+      .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(~empty), .empty(empty));
+
+   assign set_stb_o = ~empty;
+
+endmodule // settings_bus_crossclock
-- 
cgit v1.2.3


From 9899b81f920b8dab0220e2e4b086bae0f24f6970 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 11 May 2010 15:49:48 -0700
Subject: cleaned up the logic, this is copied over from quad radio

---
 usrp2/control_lib/settings_bus.v | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

(limited to 'usrp2/control_lib')

diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v
index d01a30ab4..aec179516 100644
--- a/usrp2/control_lib/settings_bus.v
+++ b/usrp2/control_lib/settings_bus.v
@@ -10,8 +10,7 @@ module settings_bus
      input wb_stb_i,
      input wb_we_i,
      output reg wb_ack_o,
-     input sys_clk,
-     output strobe,
+     output reg strobe,
      output reg [7:0] addr,
      output reg [31:0] data);
 
@@ -20,18 +19,18 @@ module settings_bus
    always @(posedge wb_clk)
      if(wb_rst)
        begin
-	  stb_int <= 1'b0;
+	  strobe <= 1'b0;
 	  addr <= 8'd0;
 	  data <= 32'd0;
        end
-     else if(wb_we_i & wb_stb_i)
+     else if(wb_we_i & wb_stb_i & ~wb_ack_o)
        begin
-	  stb_int <= 1'b1;
+	  strobe <= 1'b1;
 	  addr <= wb_adr_i[9:2];
 	  data <= wb_dat_i;
        end
      else
-       stb_int <= 1'b0;
+       strobe <= 1'b0;
 
    always @(posedge wb_clk)
      if(wb_rst)
@@ -39,11 +38,4 @@ module settings_bus
      else
        wb_ack_o <= wb_stb_i & ~wb_ack_o;
 
-   always @(posedge wb_clk)
-     stb_int_d1 <= stb_int;
-
-   //assign strobe = stb_int & ~stb_int_d1;
-   assign strobe = stb_int & wb_ack_o;
-          
 endmodule // settings_bus
-
-- 
cgit v1.2.3