From 9515a3a820cf181be9a980e89c517f1b5083eadf Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 8 Nov 2010 17:19:50 -0800 Subject: select bus is 2 bits wide --- usrp2/control_lib/fifo_to_wb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/control_lib') diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index 5be865a83..fc0f29f2d 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -5,7 +5,7 @@ module fifo_to_wb input [17:0] data_i, input src_rdy_i, output dst_rdy_o, output [17:0] data_o, output src_rdy_o, input dst_rdy_i, output reg [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, input [7:0] triggers, output [31:0] debug0, output [31:0] debug1); -- cgit v1.2.3