From 93185ca7719e8949e90b594676be6c3d2f709fb9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 11 May 2010 15:48:47 -0700 Subject: allow settings bus to cross to a new clock domain, should help timing, but not attached yet --- usrp2/control_lib/settings_bus_crossclock.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 usrp2/control_lib/settings_bus_crossclock.v (limited to 'usrp2/control_lib') diff --git a/usrp2/control_lib/settings_bus_crossclock.v b/usrp2/control_lib/settings_bus_crossclock.v new file mode 100644 index 000000000..b043aa0ad --- /dev/null +++ b/usrp2/control_lib/settings_bus_crossclock.v @@ -0,0 +1,20 @@ + + +// This module takes the settings bus on one clock domain and crosses it over to another domain +// Typically it will be used with the input settings bus on the wishbone clock, and either +// the system or dsp clock on the output side + +module settings_bus_crossclock + (input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i, + input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o); + + wire full, empty; + + fifo_xlnx_16x40_2clk settings_fifo + (.rst(rst_i), + .wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full), + .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(~empty), .empty(empty)); + + assign set_stb_o = ~empty; + +endmodule // settings_bus_crossclock -- cgit v1.2.3