From 3122c8c3d9740a2fd5e68b99df627bc632d764da Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 02:50:18 -0700 Subject: added little endian capability for gpmc to fifo and fifo to gpmc, since ARM is LE. --- usrp2/control_lib/newfifo/fifo19_to_fifo36.v | 40 ++++++++++++++----------- usrp2/control_lib/newfifo/fifo36_to_fifo19.v | 44 +++++++++++++++------------- 2 files changed, 47 insertions(+), 37 deletions(-) (limited to 'usrp2/control_lib') diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v index 5f9aeff9b..0e6bcea68 100644 --- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v +++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v @@ -1,26 +1,31 @@ +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. + module fifo19_to_fifo36 - (input clk, input reset, input clear, - input [18:0] f19_datain, - input f19_src_rdy_i, - output f19_dst_rdy_o, + #(parameter LE=0) + (input clk, input reset, input clear, + input [18:0] f19_datain, + input f19_src_rdy_i, + output f19_dst_rdy_o, - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i, - output [31:0] debug - ); + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i, + output [31:0] debug + ); - reg f36_sof, f36_eof, f36_occ; + reg f36_sof, f36_eof, f36_occ; - reg [1:0] state; - reg [15:0] dat0, dat1; + reg [1:0] state; + reg [15:0] dat0, dat1; - wire f19_sof = f19_datain[16]; - wire f19_eof = f19_datain[17]; - wire f19_occ = f19_datain[18]; + wire f19_sof = f19_datain[16]; + wire f19_eof = f19_datain[17]; + wire f19_occ = f19_datain[18]; - wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; always @(posedge clk) if(f19_src_rdy_i & ((state==0)|xfer_out)) @@ -68,7 +73,8 @@ module fifo19_to_fifo36 dat0 <= f19_datain; assign f19_dst_rdy_o = xfer_out | (state != 2); - assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; + assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : + {f36_occ,f36_eof,f36_sof,dat0,dat1}; assign f36_src_rdy_o = (state == 2); assign debug = state; diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v index de249aaeb..517a2a476 100644 --- a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v +++ b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v @@ -1,33 +1,38 @@ -module fifo36_to_fifo19 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [18:0] f19_dataout, - output f19_src_rdy_o, - input f19_dst_rdy_i ); +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. +module fifo36_to_fifo19 + #(parameter LE=0) + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + wire f36_sof = f36_datain[32]; wire f36_eof = f36_datain[33]; wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16]; assign f19_dataout[16] = phase ? 0 : f36_sof; assign f19_dataout[17] = phase ? f36_eof : half_line; assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); assign f19_src_rdy_o = f36_src_rdy_i; assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; - - wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + always @(posedge clk) if(reset) phase <= 0; @@ -36,6 +41,5 @@ module fifo36_to_fifo19 else if(f19_xfer) phase <= 1; - + endmodule // fifo36_to_fifo19 - -- cgit v1.2.3