From ed682e09b55a4f587077665e3ee62ecc7053ff53 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Jul 2010 16:10:12 -0700 Subject: very slight mods from v5 version --- usrp2/control_lib/s3a_icap_wb.v | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 usrp2/control_lib/s3a_icap_wb.v (limited to 'usrp2/control_lib/s3a_icap_wb.v') diff --git a/usrp2/control_lib/s3a_icap_wb.v b/usrp2/control_lib/s3a_icap_wb.v new file mode 100644 index 000000000..9a9db0f96 --- /dev/null +++ b/usrp2/control_lib/s3a_icap_wb.v @@ -0,0 +1,56 @@ + + +module s3a_icap_wb + (input clk, input reset, + input cyc_i, input stb_i, input we_i, output ack_o, + input [31:0] dat_i, output [31:0] dat_o); + + assign dat_o[31:8] = 24'd0; + + wire BUSY, CE, WRITE; + + reg [2:0] icap_state; + localparam ICAP_IDLE = 0; + localparam ICAP_WR0 = 1; + localparam ICAP_WR1 = 2; + localparam ICAP_RD0 = 3; + localparam ICAP_RD1 = 4; + + always @(posedge clk) + if(reset) + icap_state <= ICAP_IDLE; + else + case(icap_state) + ICAP_IDLE : + begin + if(stb_i & cyc_i) + if(we_i) + icap_state <= ICAP_WR0; + else + icap_state <= ICAP_RD0; + end + ICAP_WR0 : + icap_state <= ICAP_WR1; + ICAP_WR1 : + icap_state <= ICAP_IDLE; + ICAP_RD0 : + icap_state <= ICAP_RD1; + ICAP_RD1 : + icap_state <= ICAP_IDLE; + endcase // case (icap_state) + + assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); + assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0); + + assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); + + ICAP_SPARTAN3A ICAP_SPARTAN3A_inst + (.BUSY(BUSY), // Busy output + .O(dat_o[7:0]), // 32-bit data output + .CE(~CE), // Clock enable input + .CLK(clk), // Clock input + .I(dat_i[7:0]), // 32-bit data input + .WRITE(~WRITE) // Write input + ); + +endmodule // s3a_icap_wb -- cgit v1.2.3