From c6e8d0658dc66e9a24a87d4574c649b77ec4075d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 13:43:13 -0700 Subject: removes the icache and pipelines the reads --- usrp2/control_lib/ram_harvard.v | 71 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 usrp2/control_lib/ram_harvard.v (limited to 'usrp2/control_lib/ram_harvard.v') diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v new file mode 100644 index 000000000..6711da366 --- /dev/null +++ b/usrp2/control_lib/ram_harvard.v @@ -0,0 +1,71 @@ + + +// Dual ported, Harvard architecture, cached ram + +module ram_harvard + #(parameter AWIDTH=15, + parameter RAM_SIZE=16384, + parameter ICWIDTH=6, + parameter DCWIDTH=6) + + (input wb_clk_i, + input wb_rst_i, + // Firmware download port. + input [AWIDTH-1:0] ram_loader_adr_i, + input [31:0] ram_loader_dat_i, + input ram_loader_stb_i, + input [3:0] ram_loader_sel_i, + input ram_loader_we_i, + output ram_loader_ack_o, + input ram_loader_done_i, + // Instruction fetch port. + input [AWIDTH-1:0] if_adr, + output [31:0] if_data, + // Data access port. + input [AWIDTH-1:0] dwb_adr_i, + input [31:0] dwb_dat_i, + output [31:0] dwb_dat_o, + input dwb_we_i, + output dwb_ack_o, + input dwb_stb_i, + input [3:0] dwb_sel_i, + + input flush_icache ); + + reg ack_d1; + reg stb_d1; + + + dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) + sys_ram + (.clk(wb_clk_i), + .adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i), + .dat1_i(ram_loader_dat_i), + .dat1_o(if_data), + .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), + .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i), + .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), + .adr2_i(dwb_adr_i), + .dat2_i(dwb_dat_i), + .dat2_o(dwb_dat_o), + .we2_i(dwb_we_i), + .en2_i(dwb_stb_i), + .sel2_i(dwb_sel_i) + ); + + assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1)); + + always @(posedge wb_clk_i) + if(wb_rst_i) + ack_d1 <= 1'b0; + else + ack_d1 <= dwb_ack_o; + + always @(posedge wb_clk_i) + if(wb_rst_i) + stb_d1 <= 0; + else + stb_d1 <= dwb_stb_i; + + +endmodule // ram_harv_cache -- cgit v1.2.3 From d32cedbf00eb342d999832737f9f1ba2109ef2ad Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 24 May 2010 14:21:03 -0700 Subject: fixes from IJB from 5/24. Basically connect unconnected wires. --- usrp2/control_lib/ram_harvard.v | 2 ++ usrp2/top/u2_core/u2_core.v | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'usrp2/control_lib/ram_harvard.v') diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v index 6711da366..3c00f87c7 100644 --- a/usrp2/control_lib/ram_harvard.v +++ b/usrp2/control_lib/ram_harvard.v @@ -36,6 +36,8 @@ module ram_harvard reg stb_d1; + assign ram_loader_ack_o = ram_loader_stb_i; + dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram (.clk(wb_clk_i), diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 5e0b569cc..600bd7f3f 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -259,8 +259,9 @@ module u2_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; + wire [31:0] ram_loader_dat, if_dat; + wire [15:0] ram_loader_adr; + wire [14:0] if_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we, ram_loader_ack; wire iwb_ack, iwb_stb; -- cgit v1.2.3