From 247e36dcbace9ef06763c2c537b44c8225a9d6a7 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 12 May 2010 16:12:00 -0700
Subject: packet generator and verifier, to test gpmc and other data transfer
 stuff

---
 usrp2/control_lib/newfifo/.gitignore         |  2 +
 usrp2/control_lib/newfifo/packet_generator.v | 59 ++++++++++++++++++++++++++
 usrp2/control_lib/newfifo/packet_tb.v        | 29 +++++++++++++
 usrp2/control_lib/newfifo/packet_verifier.v  | 63 ++++++++++++++++++++++++++++
 4 files changed, 153 insertions(+)
 create mode 100644 usrp2/control_lib/newfifo/packet_generator.v
 create mode 100644 usrp2/control_lib/newfifo/packet_tb.v
 create mode 100644 usrp2/control_lib/newfifo/packet_verifier.v

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/.gitignore b/usrp2/control_lib/newfifo/.gitignore
index cba7efc8e..866f1faad 100644
--- a/usrp2/control_lib/newfifo/.gitignore
+++ b/usrp2/control_lib/newfifo/.gitignore
@@ -1 +1,3 @@
+*.vcd
+*.lxt
 a.out
diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v
new file mode 100644
index 000000000..e5bfe5b26
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_generator.v
@@ -0,0 +1,59 @@
+
+
+module packet_generator
+  (input clk, input reset, input clear,
+   output reg [7:0] data_o, output sof_o, output eof_o, 
+   output src_rdy_o, input dst_rdy_i);
+
+   localparam len = 32'd100;
+
+   reg [31:0] state;
+   reg [31:0] seq;
+   wire [31:0] crc_out;
+   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+   
+	
+   always @(posedge clk)
+     if(reset | clear)
+       seq <= 0;
+     else
+       if(eof_o & src_rdy_o & dst_rdy_i)
+	 seq <= seq + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(src_rdy_o & dst_rdy_i)
+	 if(state == (len - 1))
+	   state <= 32'hFFFF_FFFC;
+	 else
+	   state <= state + 1;
+
+   always @*
+     case(state)
+       0 :   data_o <= len[7:0];
+       1 :   data_o <= len[15:8];
+       2 :   data_o <= len[23:16];
+       3 :   data_o <= len[31:24];
+       4 :   data_o <= seq[7:0];
+       5 :   data_o <= seq[15:8];
+       6 :   data_o <= seq[23:16];
+       7 :   data_o <= seq[31:24];
+       32'hFFFF_FFFC : data_o <= crc_out[31:24];
+       32'hFFFF_FFFD : data_o <= crc_out[23:16];
+       32'hFFFF_FFFE : data_o <= crc_out[15:8];
+       32'hFFFF_FFFF : data_o <= crc_out[7:0];
+       default : data_o <= state[7:0];
+     endcase // case (state)
+   
+   assign src_rdy_o = 1;
+   assign sof_o = (state == 0);
+   assign eof_o = (state == 32'hFFFF_FFFF);
+
+   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
+	   .calc(calc_crc), .crc_out(crc_out), .match());
+   
+endmodule // packet_generator
diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+   wire [7:0] data;
+   wire       sof, eof, src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet_tb.vcd");
+   initial $dumpvars(0,packet_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			     .data_o(data), .sof_o(sof), .eof_o(eof),
+			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			    .data_i(data), .sof_i(sof), .eof_i(eof),
+			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v
new file mode 100644
index 000000000..22c924198
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_verifier.v
@@ -0,0 +1,63 @@
+
+
+// Packet format --
+//    Line 1 -- Length, 32 bits
+//    Line 2 -- Sequence number, 32 bits
+//    Last line -- CRC, 32 bits
+
+module packet_verifier
+  (input clk, input reset, input clear,
+   input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o,
+
+   output reg [31:0] total, 
+   output reg [31:0] crc_err, 
+   output reg [31:0] seq_err, 
+   output reg [31:0] len_err);
+
+   assign dst_rdy_o = ~last_byte_d1;
+
+   reg [31:0] 	     seq_num;
+   reg [31:0] 	     length;
+
+   wire 	     calc_crc = src_rdy_i & dst_rdy_o;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
+	   .calc(calc_crc), .crc_out(), .match(match_crc));
+
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
+
+   assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
+   assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+
+   // stubs for now
+   wire 	     match_seq = 1;
+   wire 	     match_len = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       last_byte_d1 <= 0;
+     else 
+       last_byte_d1 <= last_byte;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  total <= 0;
+	  crc_err <= 0;
+	  seq_err <= 0;
+	  len_err <= 0;
+       end
+     else
+       if(last_byte_d1)
+	 begin
+	    total <= total + 1;
+	    if(~match_crc)
+	      crc_err <= crc_err + 1;
+	    else if(~match_seq)
+	      seq_err <= seq_err + 1;
+	    else if(~match_len)
+	      seq_err <= len_err + 1;
+	 end
+   
+endmodule // packet_verifier
-- 
cgit v1.2.3


From b04a1beaab300000ce2d8a5814bd2e37af48286c Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 12 May 2010 18:51:33 -0700
Subject: moved fifos into gpmc_async, reorganized top level a bit, added in
 crc packet gen and test

---
 usrp2/control_lib/newfifo/packet_generator32.v | 21 ++++++
 usrp2/control_lib/newfifo/packet_verifier.v    | 10 ++-
 usrp2/control_lib/newfifo/packet_verifier32.v  | 23 +++++++
 usrp2/gpmc/gpmc_async.v                        | 91 +++++++++++++++-----------
 usrp2/top/u1e/Makefile                         |  4 ++
 usrp2/top/u1e/u1e_core.v                       | 61 ++++++++++-------
 6 files changed, 144 insertions(+), 66 deletions(-)
 create mode 100644 usrp2/control_lib/newfifo/packet_generator32.v
 create mode 100644 usrp2/control_lib/newfifo/packet_verifier32.v

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/control_lib/newfifo/packet_generator32.v
new file mode 100644
index 000000000..6f8004964
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_generator32.v
@@ -0,0 +1,21 @@
+
+
+module packet_generator32
+  (input clk, input reset, input clear,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n;
+   
+   packet_generator pkt_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
+
+   ll8_to_fifo36 ll8_to_f36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof),
+      .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n),
+      .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i));
+   
+endmodule // packet_generator32
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v
index 22c924198..b49ad1bbb 100644
--- a/usrp2/control_lib/newfifo/packet_verifier.v
+++ b/usrp2/control_lib/newfifo/packet_verifier.v
@@ -7,28 +7,26 @@
 
 module packet_verifier
   (input clk, input reset, input clear,
-   input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o,
+   input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
 
    output reg [31:0] total, 
    output reg [31:0] crc_err, 
    output reg [31:0] seq_err, 
    output reg [31:0] len_err);
 
-   assign dst_rdy_o = ~last_byte_d1;
-
    reg [31:0] 	     seq_num;
    reg [31:0] 	     length;
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
 
    wire 	     calc_crc = src_rdy_i & dst_rdy_o;
    
    crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
 	   .calc(calc_crc), .crc_out(), .match(match_crc));
 
-   wire 	     first_byte, last_byte;
-   reg 		     second_byte, last_byte_d1;
-
    assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
    assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+   assign dst_rdy_o = ~last_byte_d1;
 
    // stubs for now
    wire 	     match_seq = 1;
diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v
new file mode 100644
index 000000000..065607b6c
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet_verifier32.v
@@ -0,0 +1,23 @@
+
+
+module packet_verifier32
+  (input clk, input reset, input clear,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
+   
+   fifo36_to_ll8 f36_to_ll8
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o),
+      .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
+   
+   packet_verifier pkt_ver
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n),
+      .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_verifier32
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index dd06478b3..380689c62 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -1,37 +1,38 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module gpmc_async
-  (// GPMC signals
-   input arst,
-   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
-   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
-   
-   // GPIOs for FIFO signalling
-   output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
-   
-   // Wishbone signals
-   input wb_clk, input wb_rst,
-   output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
-   output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+  #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+   (// GPMC signals
+    input arst,
+    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+    
+    // GPIOs for FIFO signalling
+    output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
+    
+    // Wishbone signals
+    input wb_clk, input wb_rst,
+    output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+    
+    // FIFO interface
+    input fifo_clk, input fifo_rst,
+    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+    
+    input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+    
+    output [31:0] debug
+    );
 
-   // FIFO interface
-   input fifo_clk, input fifo_rst,
-   output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
-   input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-
-   input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+   wire 	  EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	  EM_D_fifo;
+   wire [15:0] 	  EM_D_wb;
    
-   output [31:0] debug
-   );
-
-   wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
-   wire [15:0] 	EM_D_fifo;
-   wire [15:0] 	EM_D_wb;
-
    assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
-
-   wire 	bus_error_tx, bus_error_rx;
-
+   
+   wire 	  bus_error_tx, bus_error_rx;
+   
    always @(posedge fifo_clk)
      if(fifo_rst)
        bus_error <= 0;
@@ -45,9 +46,11 @@ module gpmc_async
    // ////////////////////////////////////////////
    // TX Data Path
 
-   wire [17:0] 	tx18_data, tx18b_data;
-   wire 	tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
-   wire [15:0] 	tx_fifo_space;
+   wire [17:0] 	  tx18_data, tx18b_data;
+   wire 	  tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	  tx_fifo_space;
+   wire [35:0] 	  tx36_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy;
    
    gpmc_to_fifo_async gpmc_to_fifo_async
      (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
@@ -64,18 +67,30 @@ module gpmc_async
    fifo19_to_fifo36 f19_to_f36
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
-      .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
+      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
    
+   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+
    // ////////////////////////////////////////////
    // RX Data Path
-
-   wire [17:0] 	rx18_data, rx18b_data;
-   wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
-   wire [15:0] 	rx_fifo_space;
    
+   wire [17:0] 	  rx18_data, rx18b_data;
+   wire 	  rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	  rx_fifo_space;
+   wire [35:0] 	  rx36_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+
    fifo36_to_fifo18 f18_to_f36
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
       .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
 
    fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
@@ -106,6 +121,6 @@ module gpmc_async
       .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
       .wb_ack_i(wb_ack_i) );
    
-      assign debug = 0;
+   assign debug = 0;
    
 endmodule // gpmc_async
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index 2aebb33f9..8622b8480 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -111,6 +111,10 @@ control_lib/newfifo/fifo_cascade.v \
 control_lib/newfifo/fifo36_to_ll8.v \
 control_lib/newfifo/fifo36_to_fifo18.v \
 control_lib/newfifo/fifo19_to_fifo36.v \
+control_lib/newfifo/packet_generator.v \
+control_lib/newfifo/packet_verifier.v \
+control_lib/newfifo/packet_generator32.v \
+control_lib/newfifo/packet_verifier32.v \
 control_lib/longfifo.v \
 control_lib/shortfifo.v \
 control_lib/medfifo.v \
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index a262184a8..903121832 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,4 +1,9 @@
 
+
+//`define LOOPBACK 1
+//`define TIMED 1
+`define CRC 1
+
 module u1e_core
   (input clk_fpga, input rst_fpga,
    output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -61,47 +66,59 @@ module u1e_core
 
 		    .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
 		    .debug(debug_gpmc));
-/*
+
+`ifdef LOOPBACK
    fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo
      (.clk(wb_clk), .reset(wb_rst), .clear(0),
       .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
       .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-*/
-   wire 	 tx_strobe, rx_strobe, tx_enable, rx_enable;
+   wire 	 rx_sof = rx_data[32];
+   wire 	 rx_eof = rx_data[33];
+`endif // LOOPBACK
+
+`ifdef TIMED
    wire [7:0] 	 rate;
-   wire 	 tx_fifo_rdy, rx_fifo_rdy;
-   
+
+   // TX side
+   wire 	 tx_enable;
    cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable),
-			   .rate(rate), .strobe_fast(1), .strobe_slow(tx_strobe));
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(11)) tx_fifo
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
-      .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
-      .dataout(), .src_rdy_o(tx_fifo_rdy), .dst_rdy_i(tx_strobe));
+			   .rate(rate), .strobe_fast(1), .strobe_slow(tx_dst_rdy));
 
-   
+   // RX side
+   wire 	 rx_enable;
    reg [15:0] 	 ctr;
    wire [15:0] 	 rx_pkt_len = 480;
    wire 	 rx_eof = (ctr == rx_pkt_len);
    wire 	 rx_sof = (ctr == 0);
    
    cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable),
-			   .rate(rate), .strobe_fast(1), .strobe_slow(rx_strobe));
+			   .rate(rate), .strobe_fast(1), .strobe_slow(rx_src_rdy));
    
-   fifo_cascade #(.WIDTH(36), .SIZE(11)) rx_fifo
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
-      .datain({2'b00,rx_eof,rx_sof,16'd0,ctr}), .src_rdy_i(rx_strobe), .dst_rdy_o(rx_fifo_rdy),
-      .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
    always @(posedge wb_clk)
      if(wb_rst)
        ctr <= 0;
-     else if(rx_strobe & rx_fifo_rdy)
+     else if(rx_dst_rdy & rx_src_rdy)
        if(ctr == rx_pkt_len)
 	 ctr <= 0;
        else
 	 ctr <= ctr + 1;
-   
+
+   assign rx_data = {2'b00,rx_eof,rx_sof,~ctr,ctr};   
+`endif // TIMED
+
+`ifdef CRC
+   packet_generator32 pktgen32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
+   packet_verifier32 pktver32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+   wire 	 rx_sof = rx_data[32];
+   wire 	 rx_eof = rx_data[33];
+`endif // CRC   
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Intercon, single master
@@ -364,8 +381,8 @@ module u1e_core
    
    
    assign debug_gpio_0 = { debug_gpmc };
-   assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy},
-			   {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy},
+   assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
+			   {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
 			   {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
 			   {3'b0, bus_error, misc_gpio[11:0]} };
    
-- 
cgit v1.2.3


From c94256034819feb26d739e57e8cf7d3f60539e9c Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 20 May 2010 00:30:49 -0700
Subject: combined timed and crc cases.  fifo pacer produces/consumes at a
 fixed rate

---
 usrp2/control_lib/newfifo/fifo_pacer.v | 24 ++++++++++++++
 usrp2/top/u1e/Makefile                 |  1 +
 usrp2/top/u1e/u1e_core.v               | 57 ++++++++++++++--------------------
 3 files changed, 48 insertions(+), 34 deletions(-)
 create mode 100644 usrp2/control_lib/newfifo/fifo_pacer.v

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/fifo_pacer.v b/usrp2/control_lib/newfifo/fifo_pacer.v
new file mode 100644
index 000000000..1bf03ab6e
--- /dev/null
+++ b/usrp2/control_lib/newfifo/fifo_pacer.v
@@ -0,0 +1,24 @@
+
+
+module fifo_pacer
+  (input clk,
+   input reset,
+   input [7:0] rate,
+   input enable,
+   input src1_rdy_i, output dst1_rdy_o,
+   output src2_rdy_o, input dst2_rdy_i,
+   output underrun, overrun);
+
+   wire   strobe;
+   
+   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
+			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));
+
+   wire   all_ready = src1_rdy_i & dst2_rdy_i;
+   assign dst1_rdy_o = all_ready & strobe;
+   assign src2_rdy_o = dst1_rdy_o;
+
+   assign underrun = strobe & ~src1_rdy_i;
+   assign overrun = strobe & ~dst2_rdy_i;
+   
+endmodule // fifo_pacer
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index 8622b8480..0277ef4f2 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -115,6 +115,7 @@ control_lib/newfifo/packet_generator.v \
 control_lib/newfifo/packet_verifier.v \
 control_lib/newfifo/packet_generator32.v \
 control_lib/newfifo/packet_verifier32.v \
+control_lib/newfifo/fifo_pacer.v \
 control_lib/longfifo.v \
 control_lib/shortfifo.v \
 control_lib/medfifo.v \
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 903121832..21ac97dbd 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,8 +1,7 @@
 
 
 //`define LOOPBACK 1
-//`define TIMED 1
-`define CRC 1
+`define TIMED 1
 
 module u1e_core
   (input clk_fpga, input rst_fpga,
@@ -80,45 +79,35 @@ module u1e_core
    wire [7:0] 	 rate;
 
    // TX side
-   wire 	 tx_enable;
-   cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable),
-			   .rate(rate), .strobe_fast(1), .strobe_slow(tx_dst_rdy));
-
-   // RX side
-   wire 	 rx_enable;
-   reg [15:0] 	 ctr;
-   wire [15:0] 	 rx_pkt_len = 480;
-   wire 	 rx_eof = (ctr == rx_pkt_len);
-   wire 	 rx_sof = (ctr == 0);
+   wire 	 tx_enable, tx_src_rdy_int, tx_dst_rdy_int;
    
-   cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable),
-			   .rate(rate), .strobe_fast(1), .strobe_slow(rx_src_rdy));
+   fifo_pacer tx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
+      .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
+      .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
+      .underrun(tx_underrun), .overrun());
    
-   always @(posedge wb_clk)
-     if(wb_rst)
-       ctr <= 0;
-     else if(rx_dst_rdy & rx_src_rdy)
-       if(ctr == rx_pkt_len)
-	 ctr <= 0;
-       else
-	 ctr <= ctr + 1;
-
-   assign rx_data = {2'b00,rx_eof,rx_sof,~ctr,ctr};   
-`endif // TIMED
-
-`ifdef CRC
-   packet_generator32 pktgen32
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
    packet_verifier32 pktver32
      (.clk(wb_clk), .reset(wb_rst), .clear(clear),
-      .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
       .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
 
+   // RX side
+   wire 	 rx_enable, rx_src_rdy_int, rx_dst_rdy_int;
    wire 	 rx_sof = rx_data[32];
    wire 	 rx_eof = rx_data[33];
-`endif // CRC   
+
+   packet_generator32 pktgen32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
+
+   fifo_pacer rx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
+      .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
+      .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
+      .underrun(), .overrun(rx_overrun));
+   
+`endif //  `ifdef TIMED
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Intercon, single master
@@ -233,7 +222,7 @@ module u1e_core
    
    assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds;  // LEDs are arranged funny on board
    assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
-   assign { rx_overrun, tx_underrun } = 0; // reg_test;
+   //assign { rx_overrun, tx_underrun } = 0; // reg_test;
    
    assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
 			(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} :
-- 
cgit v1.2.3


From 1d38c098122746ff34c0c1f16668b44d7337175d Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 20 May 2010 16:48:59 -0700
Subject: send bigger packets to reduce cpu load

---
 usrp2/control_lib/newfifo/packet_generator.v | 2 +-
 usrp2/top/u1e/u1e_core.v                     | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v
index e5bfe5b26..6e8b45ccd 100644
--- a/usrp2/control_lib/newfifo/packet_generator.v
+++ b/usrp2/control_lib/newfifo/packet_generator.v
@@ -5,7 +5,7 @@ module packet_generator
    output reg [7:0] data_o, output sof_o, output eof_o, 
    output src_rdy_o, input dst_rdy_i);
 
-   localparam len = 32'd100;
+   localparam len = 32'd2000;
 
    reg [31:0] state;
    reg [31:0] seq;
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 48b5bd010..ee193ffb9 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -43,6 +43,7 @@ module u1e_core
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy;
    reg [15:0] 	 tx_frame_len;
    wire [15:0] 	 rx_frame_len;
+   wire [7:0] 	 rate;
 
    wire 	 bus_error;
    
@@ -76,7 +77,6 @@ module u1e_core
 `endif // LOOPBACK
 
 `ifdef TIMED
-   wire [7:0] 	 rate;
 
    // TX side
    wire 	 tx_enable, tx_src_rdy_int, tx_dst_rdy_int;
@@ -362,7 +362,7 @@ module u1e_core
 
    assign debug_clk = { EM_CLK, clk_fpga };
    assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun },
-		    { EM_A[8:1] },
+		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
 		    { EM_D } };
 
    //assign debug = { phase[23:8], txsync, txblank, tx };
-- 
cgit v1.2.3


From 268324b62898a916c0ef01e9336c34cd4ae1ff93 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 21 May 2010 15:56:01 -0700
Subject: fix double declaration

---
 usrp2/control_lib/newfifo/fifo36_to_ll8.v | 1 -
 1 file changed, 1 deletion(-)

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/fifo36_to_ll8.v b/usrp2/control_lib/newfifo/fifo36_to_ll8.v
index 0dee1dfc6..9604d0e38 100644
--- a/usrp2/control_lib/newfifo/fifo36_to_ll8.v
+++ b/usrp2/control_lib/newfifo/fifo36_to_ll8.v
@@ -55,6 +55,5 @@ module fifo36_to_ll8
 
    assign advance 	 = ll_src_rdy & ll_dst_rdy;
    assign f36_dst_rdy_o  = advance & ((state==3)|ll_eof);
-   assign debug 	 = state;
    
 endmodule // ll8_to_fifo36
-- 
cgit v1.2.3


From d3e6f630945076cc9d5fb91e86e1caf0b554ac89 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 21 May 2010 15:56:18 -0700
Subject: fifo36_to_ll8 and fifo pacer need a real fifo between them or they
 deadlock (by design)

---
 usrp2/control_lib/newfifo/packet_verifier32.v | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v
index 065607b6c..06a13d242 100644
--- a/usrp2/control_lib/newfifo/packet_verifier32.v
+++ b/usrp2/control_lib/newfifo/packet_verifier32.v
@@ -7,10 +7,17 @@ module packet_verifier32
 
    wire [7:0] 	     ll_data;
    wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
+   wire [35:0] 	     data_int;
+   wire 	     src_rdy_int, dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
    
    fifo36_to_ll8 f36_to_ll8
      (.clk(clk), .reset(reset), .clear(clear),
-      .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o),
+      .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
       .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
       .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
    
-- 
cgit v1.2.3


From 6f63773d7425dd952c5ca24da618c22c486ae294 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 24 May 2010 11:34:42 -0700
Subject: test full width packets

---
 usrp2/control_lib/newfifo/packet32_tb.v | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 usrp2/control_lib/newfifo/packet32_tb.v

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/packet32_tb.v b/usrp2/control_lib/newfifo/packet32_tb.v
new file mode 100644
index 000000000..82bb09c29
--- /dev/null
+++ b/usrp2/control_lib/newfifo/packet32_tb.v
@@ -0,0 +1,27 @@
+
+
+module packet32_tb();
+
+   wire [35:0] data;
+   wire       src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet32_tb.vcd");
+   initial $dumpvars(0,packet32_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet32_tb
-- 
cgit v1.2.3


From 761e22013c6715987c411216d012098e60684836 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 6 Jun 2010 02:26:48 -0700
Subject: get rid of redundant fifo18, since we can just use fifo19 and ignore
 the occ bit

---
 usrp2/control_lib/newfifo/fifo36_to_fifo18.v | 40 ----------------------------
 usrp2/gpmc/gpmc_async.v                      |  5 ++--
 usrp2/gpmc/gpmc_sync.v                       |  5 ++--
 3 files changed, 6 insertions(+), 44 deletions(-)
 delete mode 100644 usrp2/control_lib/newfifo/fifo36_to_fifo18.v

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v b/usrp2/control_lib/newfifo/fifo36_to_fifo18.v
deleted file mode 100644
index b636ab9ca..000000000
--- a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v
+++ /dev/null
@@ -1,40 +0,0 @@
-
-module fifo36_to_fifo18
-  (input clk, input reset, input clear,
-   input [35:0] f36_datain,
-   input f36_src_rdy_i,
-   output f36_dst_rdy_o,
-   
-   output [17:0] f18_dataout,
-   output f18_src_rdy_o,
-   input f18_dst_rdy_i );
-
-   wire   f36_sof  = f36_datain[32];
-   wire   f36_eof  = f36_datain[33];
-   wire   f36_occ  = f36_datain[35:34];
-
-   reg phase;
-
-   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
-   
-   assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
-   assign f18_dataout[16]  = phase ? 0 : f36_sof;
-   assign f18_dataout[17]  = phase ? f36_eof : half_line;
-   
-   assign f18_src_rdy_o    = f36_src_rdy_i;
-   assign f36_dst_rdy_o    = (phase | half_line) & f18_dst_rdy_i;
-	
-   wire f18_xfer 	   = f18_src_rdy_o & f18_dst_rdy_i;
-   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
-
-   always @(posedge clk)
-     if(reset)
-       phase 		  <= 0;
-     else if(f36_xfer)
-       phase 		  <= 0;
-     else if(f18_xfer)
-       phase 		  <= 1;
-   
-       
-endmodule // fifo36_to_fifo18
-
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index 380689c62..f42b835ed 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -82,16 +82,17 @@ module gpmc_async
    wire [15:0] 	  rx_fifo_space;
    wire [35:0] 	  rx36_data;
    wire 	  rx36_src_rdy, rx36_dst_rdy;
+   wire 	  dummy;
    
    fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
      (.clk(wb_clk), .reset(wb_rst), .clear(0),
       .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
       .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
 
-   fifo36_to_fifo18 f18_to_f36
+   fifo36_to_fifo19 f36_to_f19
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
-      .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
+      .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
 
    fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v
index 825d131d8..bac489ca0 100644
--- a/usrp2/gpmc/gpmc_sync.v
+++ b/usrp2/gpmc/gpmc_sync.v
@@ -68,11 +68,12 @@ module gpmc_sync
    wire [17:0] 	rx18_data, rx18b_data;
    wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
    wire [15:0] 	rx_fifo_space, rx_frame_len;
+   wire 	dummy;
    
-   fifo36_to_fifo18 f18_to_f36
+   fifo36_to_fifo19 f36_to_f19
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
-      .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
+      .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
 
    fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo
      (.wclk(fifo_clk), .datain(rx18_data), 
-- 
cgit v1.2.3


From 3122c8c3d9740a2fd5e68b99df627bc632d764da Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 6 Jun 2010 02:50:18 -0700
Subject: added little endian capability for gpmc to fifo and fifo to gpmc,
 since ARM is LE.

---
 usrp2/control_lib/newfifo/fifo19_to_fifo36.v | 40 ++++++++++++++-----------
 usrp2/control_lib/newfifo/fifo36_to_fifo19.v | 44 +++++++++++++++-------------
 usrp2/gpmc/gpmc_async.v                      |  4 +--
 usrp2/gpmc/gpmc_sync.v                       |  4 +--
 4 files changed, 51 insertions(+), 41 deletions(-)

(limited to 'usrp2/control_lib/newfifo')

diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
index 5f9aeff9b..0e6bcea68 100644
--- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
@@ -1,26 +1,31 @@
 
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+
 module fifo19_to_fifo36
-  (input clk, input reset, input clear,
-   input [18:0] f19_datain,
-   input f19_src_rdy_i,
-   output f19_dst_rdy_o,
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [18:0] f19_datain,
+    input f19_src_rdy_i,
+    output f19_dst_rdy_o,
 
-   output [35:0] f36_dataout,
-   output f36_src_rdy_o,
-   input f36_dst_rdy_i,
-   output [31:0] debug
-   );
+    output [35:0] f36_dataout,
+    output f36_src_rdy_o,
+    input f36_dst_rdy_i,
+    output [31:0] debug
+    );
 
-   reg 	 f36_sof, f36_eof, f36_occ;
+   reg 		  f36_sof, f36_eof, f36_occ;
    
-   reg [1:0] state;
-   reg [15:0] dat0, dat1;
+   reg [1:0] 	  state;
+   reg [15:0] 	  dat0, dat1;
 
-   wire f19_sof  = f19_datain[16];
-   wire f19_eof  = f19_datain[17];
-   wire f19_occ  = f19_datain[18];
+   wire 	  f19_sof  = f19_datain[16];
+   wire 	  f19_eof  = f19_datain[17];
+   wire 	  f19_occ  = f19_datain[18];
 
-   wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+   wire 	  xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
 
    always @(posedge clk)
      if(f19_src_rdy_i & ((state==0)|xfer_out))
@@ -68,7 +73,8 @@ module fifo19_to_fifo36
        dat0 		   <= f19_datain;
    
    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
-   assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+   assign    f36_dataout    = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
+			      {f36_occ,f36_eof,f36_sof,dat0,dat1};
    assign    f36_src_rdy_o  = (state == 2);
 
    assign    debug = state;
diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
index de249aaeb..517a2a476 100644
--- a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
+++ b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
@@ -1,33 +1,38 @@
 
-module fifo36_to_fifo19
-  (input clk, input reset, input clear,
-   input [35:0] f36_datain,
-   input f36_src_rdy_i,
-   output f36_dst_rdy_o,
-   
-   output [18:0] f19_dataout,
-   output f19_src_rdy_o,
-   input f19_dst_rdy_i );
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
 
+module fifo36_to_fifo19
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [35:0] f36_datain,
+    input f36_src_rdy_i,
+    output f36_dst_rdy_o,
+    
+    output [18:0] f19_dataout,
+    output f19_src_rdy_o,
+    input f19_dst_rdy_i );
+   
    wire   f36_sof  = f36_datain[32];
    wire   f36_eof  = f36_datain[33];
    wire   f36_occ  = f36_datain[35:34];
-
-   reg phase;
-
-   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
    
-   assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+   reg 	  phase;
+   
+   wire   half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
+   
+   assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16];
    assign f19_dataout[16]  = phase ? 0 : f36_sof;
    assign f19_dataout[17]  = phase ? f36_eof : half_line;
    assign f19_dataout[18]  = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
    
    assign f19_src_rdy_o    = f36_src_rdy_i;
    assign f36_dst_rdy_o    = (phase | half_line) & f19_dst_rdy_i;
-	
-   wire f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
-
+   
+   wire   f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire   f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+   
    always @(posedge clk)
      if(reset)
        phase 		  <= 0;
@@ -36,6 +41,5 @@ module fifo36_to_fifo19
      else if(f19_xfer)
        phase 		  <= 1;
    
-       
+   
 endmodule // fifo36_to_fifo19
-
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index f42b835ed..1050cef7d 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -64,7 +64,7 @@ module gpmc_async
       .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
       .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
 
-   fifo19_to_fifo36 f19_to_f36
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
       .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
@@ -89,7 +89,7 @@ module gpmc_async
       .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
       .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
 
-   fifo36_to_fifo19 f36_to_f19
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
       .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v
index bac489ca0..61c54a793 100644
--- a/usrp2/gpmc/gpmc_sync.v
+++ b/usrp2/gpmc/gpmc_sync.v
@@ -57,7 +57,7 @@ module gpmc_sync
       .rclk(fifo_clk), .dataout(tx18b_data), 
       .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst));
 
-   fifo19_to_fifo36 f19_to_f36
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
       .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
@@ -70,7 +70,7 @@ module gpmc_sync
    wire [15:0] 	rx_fifo_space, rx_frame_len;
    wire 	dummy;
    
-   fifo36_to_fifo19 f36_to_f19
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
      (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
       .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
       .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
-- 
cgit v1.2.3