From dbeea34b66c939c15eaaa0a9f805ee9286d0a878 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 19 Jul 2011 10:29:57 -0700 Subject: removed wb readback of ATR, allowing it to be synthesized as luts --- usrp2/control_lib/atr_controller16.v | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'usrp2/control_lib/atr_controller16.v') diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v index ff4f634c7..a2ebd1dde 100644 --- a/usrp2/control_lib/atr_controller16.v +++ b/usrp2/control_lib/atr_controller16.v @@ -47,8 +47,11 @@ module atr_controller16 atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; end // if (we_i & stb_i & cyc_i) - always @(posedge clk_i) - dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + // Removing readback allows ram to be synthesized as LUTs instead of regs + //always @(posedge clk_i) + // dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + always @* + dat_o <= 16'd0; always @(posedge clk_i) ack_o <= stb_i & cyc_i & ~ack_o; -- cgit v1.2.3