From a170b9b42345794429486dd4f3316e84ea2cc871 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Fri, 22 Jan 2010 11:46:58 -0800
Subject: Moved usrp1 fpga files into usrp1 subdir.

---
 usrp1/models/bustri.v | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 usrp1/models/bustri.v

(limited to 'usrp1/models/bustri.v')

diff --git a/usrp1/models/bustri.v b/usrp1/models/bustri.v
new file mode 100644
index 000000000..6e5a0f74c
--- /dev/null
+++ b/usrp1/models/bustri.v
@@ -0,0 +1,17 @@
+
+// Model for tristate bus on altera
+// FIXME do we really need to use a megacell for this?
+
+module bustri (data,
+	       enabledt,
+	       tridata);
+   
+   input [15:0]  data;
+   input 	 enabledt;
+   inout [15:0]  tridata;
+   
+   assign 	 tridata = enabledt ? data :16'bz;
+   
+endmodule // bustri
+
+
-- 
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