From a170b9b42345794429486dd4f3316e84ea2cc871 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 11:46:58 -0800 Subject: Moved usrp1 fpga files into usrp1 subdir. --- usrp1/megacells/pll_bb.v | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 usrp1/megacells/pll_bb.v (limited to 'usrp1/megacells/pll_bb.v') diff --git a/usrp1/megacells/pll_bb.v b/usrp1/megacells/pll_bb.v new file mode 100644 index 000000000..debadaa25 --- /dev/null +++ b/usrp1/megacells/pll_bb.v @@ -0,0 +1,29 @@ +//Copyright (C) 1991-2004 Altera Corporation +//Any megafunction design, and related netlist (encrypted or decrypted), +//support information, device programming or simulation file, and any other +//associated documentation or information provided by Altera or a partner +//under Altera's Megafunction Partnership Program may be used only +//to program PLD devices (but not masked PLD devices) from Altera. Any +//other use of such megafunction design, netlist, support information, +//device programming or simulation file, or any other related documentation +//or information is prohibited for any other purpose, including, but not +//limited to modification, reverse engineering, de-compiling, or use with +//any other silicon devices, unless such use is explicitly licensed under +//a separate agreement with Altera or a megafunction partner. Title to the +//intellectual property, including patents, copyrights, trademarks, trade +//secrets, or maskworks, embodied in any such megafunction design, netlist, +//support information, device programming or simulation file, or any other +//related documentation or information provided by Altera or a megafunction +//partner, remains with Altera, the megafunction partner, or their respective +//licensors. No other licenses, including any licenses needed under any third +//party's intellectual property, are provided herein. + +module pll ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + -- cgit v1.2.3