From a170b9b42345794429486dd4f3316e84ea2cc871 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Fri, 22 Jan 2010 11:46:58 -0800
Subject: Moved usrp1 fpga files into usrp1 subdir.

---
 usrp1/megacells/fifo_4kx16_dc.inc | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100755 usrp1/megacells/fifo_4kx16_dc.inc

(limited to 'usrp1/megacells/fifo_4kx16_dc.inc')

diff --git a/usrp1/megacells/fifo_4kx16_dc.inc b/usrp1/megacells/fifo_4kx16_dc.inc
new file mode 100755
index 000000000..c14c01836
--- /dev/null
+++ b/usrp1/megacells/fifo_4kx16_dc.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION fifo_4kx16_dc 
+(
+	aclr,
+	data[15..0],
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq
+)
+
+RETURNS (
+	q[15..0],
+	rdempty,
+	rdusedw[11..0],
+	wrfull,
+	wrusedw[11..0]
+);
-- 
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