From 5a17f48e7374466b10787ef2721166b1bb862cf1 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Mon, 16 Apr 2007 21:30:13 +0000 Subject: Adds capability to independently delay the Auto T/R switching signal by a configurable number of clock ticks, to allow users to precisely align their T/R output with the pipeline delays in the transmitter. There are two new registers: FR_ATR_TX_DELAY (7'd2) FR_ATR_RX_DELAY (7'd3) ...and the corresponding db_base.py methods to set them: db_base.set_atr_tx_delay(clock_ticks) db_base.set_atr_rx_delay(clock_ticks) These methods are inherited by all the daughterboard objects so you can call them from your scripts as: subdev.set_atr_tx_delay(...) ...where 'subdev' represents the daughtercard object you're working with. The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%, with no additional synthesis messages or impact on timing. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5 --- toplevel/usrp_std/usrp_std.qsf | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'toplevel') diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index ad98b1165..14dbd30c2 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 6.1 +set_global_assignment -name LAST_QUARTUS_VERSION 7.0 # Pin & Location Assignments # ========================== @@ -368,6 +368,9 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_std) # -------------------- +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -- cgit v1.2.3