From 91636cbac2b3edfba45321f1050d0b90b34ab696 Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Mon, 31 Aug 2009 12:08:30 -0700 Subject: Merged SVN matt/new_eth r10782:11633 into new_eth * svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz. --- top/u2_core/u2_core.v | 136 ++++++++++++++++++-------------------------------- top/u2_rev3/Makefile | 22 +++++++- 2 files changed, 68 insertions(+), 90 deletions(-) (limited to 'top') diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index f12b5af4d..75468a2e8 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -307,19 +307,21 @@ module u2_core .in(set_data),.out(),.changed(flush_icache)); // Buffer Pool, slave #1 - wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; - wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; - wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; - wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - buffer_pool buffer_pool + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), @@ -330,25 +332,17 @@ module u2_core .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - + // Write Interfaces - .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), - .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), - .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), - .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), - .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), - .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), - .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), - .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), // Read Interfaces - .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), - .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), - .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), - .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), - .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), - .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), - .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), - .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) ); // SPI -- Slave #2 @@ -398,11 +392,30 @@ module u2_core .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) ); - assign s5_err = 1'b0; - assign s5_rty = 1'b0; + assign s5_err = 1'b0; + assign s5_rty = 1'b0; + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 - // Slave, #6 Ethernet MAC, see below + simple_gemac_wrapper simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .pause_req(0), .pause_time(0), + .sys_clk(dsp_clk), + .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC) ); + + assign s6_err = 1'b0; + assign s6_rty = 1'b0; + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), @@ -447,55 +460,6 @@ module u2_core assign leds = (led_src & led_hw) | (~led_src & led_sw); - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; - wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; - wire [31:0] Tx_mac_data, Rx_mac_data; - wire [1:0] Tx_mac_BE, Rx_mac_BE; - wire rst_mac; - - oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); - - MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) - MAC_top - (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), - .rst_mac(rst_mac),.rst_user(dsp_rst), - .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), - .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), - .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), - .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), - .Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), - .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), - .debug0(debug_mac0),.debug1(debug_mac1) ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - mac_rxfifo_int mac_rxfifo_int - (.clk(dsp_clk),.rst(dsp_rst), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), - .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), - .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), - .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), - .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); - - mac_txfifo_int mac_txfifo_int - (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), - .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), - .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); - // ///////////////////////////////////////////////////////////////////////// // Interrupt Controller, Slave #8 @@ -546,7 +510,7 @@ module u2_core (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + .run_rx(run_rx_d1),.run_tx(run_tx),.master_time(), .ctrl_lines(atr_lines) ); assign s11_err = 0; assign s11_rty = 0; @@ -591,8 +555,7 @@ module u2_core (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), - .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), + .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), .debug_rx(debug_rx) ); @@ -602,15 +565,14 @@ module u2_core (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), .debug(debug_rx_dsp) ); tx_control #(.FIFOSIZE(10)) tx_control (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), - .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), + .rd_dat_i(rd1_dat), .rd_flags_i(rd_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), .debug(debug_txc) ); @@ -629,11 +591,9 @@ module u2_core serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), - .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), - .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile index c41ce7f77..5d782b610 100644 --- a/top/u2_rev3/Makefile +++ b/top/u2_rev3/Makefile @@ -56,14 +56,16 @@ export SOURCES := \ control_lib/CRC16_D16.v \ control_lib/atr_controller.v \ control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ control_lib/cascadefifo2.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ control_lib/dpram32.v \ control_lib/fifo_2clock.v \ control_lib/fifo_2clock_casc.v \ +control_lib/newfifo/newfifo_2clock.v \ +control_lib/newfifo/cascadefifo_2clock.v \ control_lib/gray2bin.v \ control_lib/gray_send.v \ control_lib/icache.v \ @@ -89,6 +91,22 @@ control_lib/oneshot_2clk.v \ control_lib/sd_spi.v \ control_lib/sd_spi_wb.v \ control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/address_filter.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo36_to_ll8.v \ coregen/fifo_xlnx_2Kx36_2clk.v \ coregen/fifo_xlnx_2Kx36_2clk.xco \ coregen/fifo_xlnx_512x36_2clk.v \ -- cgit v1.2.3 From 1c68af83c84fb0a03fc8ac0df6491d865287daae Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 2 Sep 2009 17:04:53 -0700 Subject: debug pins, cleaned ignores --- simple_gemac/.gitignore | 1 - top/u2_core/.gitignore | 1 + top/u2_core/u2_core.v | 29 +++++++++++++++++++++-------- 3 files changed, 22 insertions(+), 9 deletions(-) (limited to 'top') diff --git a/simple_gemac/.gitignore b/simple_gemac/.gitignore index 61e120cff..515552fdb 100644 --- a/simple_gemac/.gitignore +++ b/simple_gemac/.gitignore @@ -1,3 +1,2 @@ /a.out -/*~ /*.vcd diff --git a/top/u2_core/.gitignore b/top/u2_core/.gitignore index b30397081..9728395c1 100644 --- a/top/u2_core/.gitignore +++ b/top/u2_core/.gitignore @@ -1,3 +1,4 @@ +*~ /xst /_ngo /_xmsgs diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 75468a2e8..7fc2ce83b 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -149,7 +149,7 @@ module u2_core wire [31:0] debug_gpio_0, debug_gpio_1; wire [31:0] atr_lines; - wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; @@ -410,7 +410,8 @@ module u2_core .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), - .mdio(MDIO), .mdc(MDC) ); + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); assign s6_err = 1'b0; assign s6_rty = 1'b0; @@ -658,12 +659,24 @@ module u2_core eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - assign debug_clk[0] = 0; - assign debug_clk[1] = dsp_clk; - - assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; + assign debug_clk[0] = wb_clk; + assign debug_clk[1] = clk_to_mac; +/* + + wire mdio_cpy = MDIO; + assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, + { s6_adr[15:8] }, + { s6_adr[7:0] }, + { 6'd0, mdio_cpy, MDC } }; +*/ + + assign debug = { { GMII_TXD }, + { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, + { wr2_flags, rd2_flags }, + { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + + assign debug_gpio_0 = debug_mac; //eth_mac_debug; + assign debug_gpio_1 = 0; endmodule // u2_core -- cgit v1.2.3 From 5ce99ee61bad4f9c421a873aa2f3144e8e2aebe7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 3 Sep 2009 14:13:44 -0700 Subject: MAC transmit seems to work now. The root cause of the problem was accidentally using the rx_clk in one stage of the fifos on the tx side. --- control_lib/newfifo/fifo_2clock.v | 33 ++++++++++++++------ simple_gemac/simple_gemac_wrapper.v | 31 ++++++++++++------- simple_gemac/simple_gemac_wrapper_tb.v | 17 ++++++----- top/u2_rev3/Makefile | 56 +++++++++++----------------------- 4 files changed, 70 insertions(+), 67 deletions(-) (limited to 'top') diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v index 40c479db7..2ada39fb0 100644 --- a/control_lib/newfifo/fifo_2clock.v +++ b/control_lib/newfifo/fifo_2clock.v @@ -2,26 +2,39 @@ // FIXME ignores the AWIDTH (fifo size) parameter module fifo_2clock - #(parameter WIDTH=32, SIZE=9) + #(parameter WIDTH=36, SIZE=6) (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input arst); - wire [SIZE-1:0] level_rclk, level_wclk; - wire full, empty, write, read; + wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels + wire full, empty, write, read; assign dst_rdy_o = ~full; assign src_rdy_o = ~empty; assign write = src_rdy_i & dst_rdy_o; assign read = src_rdy_o & dst_rdy_i; - - fifo_xlnx_512x36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - assign occupied = {{(16-SIZE){1'b0}},level_rclk}; - assign space = ((1< Date: Thu, 3 Sep 2009 21:39:48 -0700 Subject: seems to build a decent fpga, but still some issues with a full connection. --- sdr_lib/rx_control.v | 39 +++++++++++++++++---------------------- sdr_lib/tx_control.v | 20 ++++++++++++++++---- top/u2_core/u2_core.v | 6 +++--- 3 files changed, 36 insertions(+), 29 deletions(-) (limited to 'top') diff --git a/sdr_lib/rx_control.v b/sdr_lib/rx_control.v index ae821e822..0adeb0794 100644 --- a/sdr_lib/rx_control.v +++ b/sdr_lib/rx_control.v @@ -63,22 +63,17 @@ module rx_control .read(read_ctrl), .empty(empty_ctrl) ); // Buffer interface to internal FIFO - wire write, full, read, empty; - wire sop_o, eop_o; - assign wr_flags_o = {2'b00, eop_o, sop_o}; - assign wr_ready_o = ~empty; - assign read = wr_ready_i & wr_ready_o; - - wire [33:0] fifo_line; + wire have_space, write; + wire [35:0] fifo_line; // Internal FIFO, size 9 is 2K, size 10 is 4K - cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo - (.clk(clk),.rst(rst),.clear(clear_overrun), - .datain(fifo_line), .write(write), .full(full), - .dataout({sop_o,eop_o,wr_dat_o}), .read(read), .empty(empty), + fifo_cascade #(.WIDTH(36),.SIZE(FIFOSIZE)) rxfifo + (.clk(clk),.reset(rst),.clear(clear_overrun), + .datain(fifo_line), .src_rdy_i(write), .dst_rdy_o(have_space), + .dataout({wr_flags_o,wr_dat_o}), .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .space(),.occupied(fifo_occupied) ); - assign fifo_full = full; - assign fifo_empty = empty; + assign fifo_full = ~have_space; + assign fifo_empty = ~wr_ready_o; // Internal FIFO to DSP interface reg [22:0] lines_left; @@ -133,13 +128,13 @@ module rx_control else if(too_late) ibs_state <= IBS_OVERRUN; IBS_FIRSTLINE : - if(full | strobe) + if(~have_space | strobe) ibs_state <= IBS_OVERRUN; else ibs_state <= IBS_RUNNING; IBS_RUNNING : if(strobe) - if(full) + if(~have_space) ibs_state <= IBS_OVERRUN; else begin @@ -165,21 +160,21 @@ module rx_control end else lines_left_frame <= lines_left_frame - 1; - end // else: !if(full) + end // else: !if(~have_space) endcase // case(ibs_state) - assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {1'b1,1'b0,master_time} : - {1'b0,((lines_left==1)|(lines_left_frame==1)),sample}; + assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {2'b0,1'b0,1'b1,master_time} : + {2'b0,((lines_left==1)|(lines_left_frame==1)),1'b0,sample}; - assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & ~full; // & (ibs_state == IBS_RUNNING) should strobe only when running + assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & have_space; // & (ibs_state == IBS_RUNNING) should strobe only when running assign overrun = (ibs_state == IBS_OVERRUN); assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE); assign read_ctrl = ( (ibs_state == IBS_IDLE) | - ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) + ((ibs_state == IBS_RUNNING) & strobe & have_space & (lines_left==1) & chain) ) & ~empty_ctrl; assign debug_rx = { 8'd0, - 1'd0, send_imm, chain, wr_ready_i,wr_ready_o, eop_o, sop_o, run, - write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl, + 1'd0, send_imm, chain, wr_ready_i,wr_ready_o, 2'b0, run, + write,have_space,wr_flags_o[1:0],write_ctrl,full_ctrl,read_ctrl,empty_ctrl, sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] }; endmodule // rx_control diff --git a/sdr_lib/tx_control.v b/sdr_lib/tx_control.v index 8766afd8b..e5fed0b93 100644 --- a/sdr_lib/tx_control.v +++ b/sdr_lib/tx_control.v @@ -64,22 +64,34 @@ module tx_control if(rd_eop_i) xfer_state <= XFER_IDLE; endcase // case(xfer_state) + + wire have_data_space; + assign full_data = ~have_data_space; - assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o; - assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o; + assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o; + assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o; - assign rd_ready_o = ~full_data & ~full_ctrl; + assign rd_ready_o = ~full_data & ~full_ctrl; wire [31:0] data_o; wire eop_o, eob, sob, send_imm; wire [31:0] sendtime; wire [4:0] occ_ctrl; - +/* cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo (.clk(clk),.rst(rst),.clear(clear_state), .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data), .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data), .space(), .occupied(fifo_occupied) ); +*/ + wire have_data; + assign empty_data = ~have_data; + + fifo_cascade #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo + (.clk(clk),.reset(rst),.clear(clear_state), + .datain({rd_eop_i,rd_dat_i[31:0]}), .src_rdy_i(write_data), .dst_rdy_o(have_data_space), + .dataout({eop_o,data_o}), .src_rdy_o(have_data), .dst_rdy_i(read_data), + .space(), .occupied(fifo_occupied) ); assign fifo_full = full_data; assign fifo_empty = empty_data; diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 7fc2ce83b..a6596eb90 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -588,7 +588,7 @@ module u2_core // /////////////////////////////////////////////////////////////////////////////////// // SERDES - +/* serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), @@ -598,7 +598,7 @@ module u2_core .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - +*/ // /////////////////////////////////////////////////////////////////////////////////// // External RAM Interface @@ -659,7 +659,7 @@ module u2_core eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - assign debug_clk[0] = wb_clk; + assign debug_clk[0] = 0; // wb_clk; assign debug_clk[1] = clk_to_mac; /* -- cgit v1.2.3 From 5743af6bd275897d68ab1177cae06045bbc402ab Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Sep 2009 16:37:29 -0700 Subject: debug the rx side --- top/u2_core/u2_core.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'top') diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index a6596eb90..cd0800afc 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -669,11 +669,16 @@ module u2_core { s6_adr[7:0] }, { 6'd0, mdio_cpy, MDC } }; */ - +/* assign debug = { { GMII_TXD }, { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, { wr2_flags, rd2_flags }, { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + */ + assign debug = { { GMII_RXD }, + { 1'd0, debug_mac2[3:0], GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { wr2_flags, rd2_flags }, + { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; assign debug_gpio_0 = debug_mac; //eth_mac_debug; assign debug_gpio_1 = 0; -- cgit v1.2.3 From 71babf966d8cd340eb62122a297c2cc3b1294b82 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Sep 2009 22:20:19 -0700 Subject: parameterized fifo sizes, some reformatting --- simple_gemac/simple_gemac_wrapper.v | 106 +++++++++++++++++++----------------- top/u2_core/u2_core.v | 5 +- 2 files changed, 57 insertions(+), 54 deletions(-) (limited to 'top') diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index 8da77f096..de445476c 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -1,44 +1,46 @@ module simple_gemac_wrapper - (input clk125, input reset, - // GMII - output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - - // Flow Control Interface - input pause_req, input [15:0] pause_time, - - // Client FIFO Interfaces - input sys_clk, - output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, - input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, - - // Wishbone Interface - input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, - input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, - - // MIIM - inout mdio, output mdc, - output [31:0] debug); - - wire [7:0] rx_data, tx_data; - wire tx_clk, tx_valid, tx_error, tx_ack; - wire rx_clk, rx_valid, rx_error, rx_ack; - - wire [47:0] ucast_addr, mcast_addr; - wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en; - - wire rst_rxclk, rst_txclk; + #(parameter RXFIFOSIZE=9, + parameter TXFIFOSIZE=6) + (input clk125, input reset, + // GMII + output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, + input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, + + // Client FIFO Interfaces + input sys_clk, + output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, + input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, + + // Wishbone Interface + input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, + input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, + + // MIIM + inout mdio, output mdc, + output [31:0] debug); + + wire [7:0] rx_data, tx_data; + wire tx_clk, tx_valid, tx_error, tx_ack; + wire rx_clk, rx_valid, rx_error, rx_ack; + + wire [47:0] ucast_addr, mcast_addr; + wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; + wire pause_request_en, pause_respect_en; + wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; + + wire tx_reset, rx_reset; reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset)); reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset)); - + simple_gemac simple_gemac (.clk125(clk125), .reset(reset), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .pause_en(pause_en), + .pause_req(pause_req), .pause_time_req(pause_time_req), + .pause_respect_en(pause_respect_en), .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), .pass_pause(pass_pause), .pass_all(pass_all), @@ -55,18 +57,20 @@ module simple_gemac_wrapper .mdio(mdio), .mdc(mdc), .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) ); + .pass_pause(pass_pause), .pass_all(pass_all), + .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en), + .pause_time(pause_time), .pause_thresh(pause_thresh) ); // RX FIFO Chain - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; - wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; - - wire [7:0] rx_ll_data, rx_ll_data2; - - wire [35:0] rx_f36_data_int1; - wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; + wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + + wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; + wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; + + wire [7:0] rx_ll_data, rx_ll_data2; + + wire [35:0] rx_f36_data_int1; + wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), @@ -92,21 +96,21 @@ module simple_gemac_wrapper .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1)); - fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) rx_2clk_fifo + fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo (.wclk(rx_clk), .datain(rx_f36_data_int1), - .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(), + .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space), .rclk(sys_clk), .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset)); // TX FIFO Chain - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; - wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; - wire [7:0] tx_ll_data, tx_ll_data2; - wire [35:0] tx_f36_data_int1; - wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; - - fifo_2clock #(.WIDTH(36), .SIZE(6)) tx_2clk_fifo + wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; + wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; + wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; + wire [7:0] tx_ll_data, tx_ll_data2; + wire [35:0] tx_f36_data_int1; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + + fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index cd0800afc..918215093 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -398,13 +398,12 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - simple_gemac_wrapper simple_gemac_wrapper + simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(0), .pause_time(0), .sys_clk(dsp_clk), .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), @@ -676,7 +675,7 @@ module u2_core { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; */ assign debug = { { GMII_RXD }, - { 1'd0, debug_mac2[3:0], GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, { wr2_flags, rd2_flags }, { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; -- cgit v1.2.3 From c21464b1107295575afa958e34f915f7d9985c14 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Sep 2009 22:23:27 -0700 Subject: Implement Eth flow control using pause frames Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though. --- simple_gemac/flow_ctrl_rx.v | 105 ++++++++++++++---------------------- simple_gemac/simple_gemac.v | 6 +-- simple_gemac/simple_gemac_wb.v | 20 +++++-- simple_gemac/simple_gemac_wrapper.v | 7 ++- top/u2_rev3/Makefile | 1 + 5 files changed, 66 insertions(+), 73 deletions(-) (limited to 'top') diff --git a/simple_gemac/flow_ctrl_rx.v b/simple_gemac/flow_ctrl_rx.v index 7ded9e08b..b13334d0e 100644 --- a/simple_gemac/flow_ctrl_rx.v +++ b/simple_gemac/flow_ctrl_rx.v @@ -2,84 +2,59 @@ // RX side of flow control -- when we are running out of RX space, send a PAUSE module flow_ctrl_rx - (input rst, - //host processor - input pause_frame_send_en, - input [15:0] pause_quanta_set, - input [15:0] fc_hwmark, - input [15:0] fc_lwmark, - // From MAC_rx_ctrl - input rx_clk, - input [15:0] rx_fifo_space, - // MAC_tx_ctrl - input tx_clk, - output reg xoff_gen, - output reg xon_gen, - input xoff_gen_complete, - input xon_gen_complete + (input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh, + input rx_clk, input rx_reset, input [15:0] rx_fifo_space, + input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req ); // ****************************************************************************** // Force our TX to send a PAUSE frame because our RX is nearly full // ****************************************************************************** - reg xon_int, xoff_int; + // RX Clock Domain + reg xon, xoff; reg [21:0] countdown; - - always @(posedge rx_clk or posedge rst) - if(rst) - begin - xon_int <= 0; - xoff_int <= 0; - end - else - begin - xon_int <= 0; - xoff_int <= 0; - if(pause_frame_send_en) - if(countdown == 0) - if(rx_fifo_space < fc_lwmark) - xoff_int <= 1; - else - ; - else - if(rx_fifo_space > fc_hwmark) - xon_int <= 1; - end // else: !if(rst) - - reg xoff_int_d1, xon_int_d1; - always @(posedge rx_clk) - xon_int_d1 <= xon_int; - always @(posedge rx_clk) - xoff_int_d1 <= xoff_int; + wire [15:0] pause_low_thresh = pause_thresh; + wire [15:0] pause_hi_thresh = 16'hFFFF; + wire [21:0] pq_reduced = {pause_time,6'd0} - 1700; - always @ (posedge tx_clk or posedge rst) - if (rst) - xoff_gen <=0; - else if (xoff_gen_complete) - xoff_gen <=0; - else if (xoff_int | xoff_int_d1) - xoff_gen <=1; + always @(posedge rx_clk) + if(rx_reset) + xoff <= 0; + else + xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh)); - always @ (posedge tx_clk or posedge rst) - if (rst) - xon_gen <=0; - else if (xon_gen_complete) - xon_gen <=0; - else if (xon_int | xon_int_d1) - xon_gen <=1; - - wire [15:0] pq_reduced = pause_quanta_set - 2; + always @(posedge rx_clk) + if(rx_reset) + xon <= 0; + else + xon <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh)); - always @(posedge tx_clk or posedge rst) - if(rst) + always @(posedge rx_clk) + if(rx_reset) countdown <= 0; - else if(xoff_gen) - countdown <= {pq_reduced,6'd0}; - else if(xon_gen) + else if(xoff) + countdown <= pq_reduced; + else if(xon) countdown <= 0; else if(countdown != 0) countdown <= countdown - 1; + + // Cross clock domains + oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx)); + oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx)); + + always @(posedge tx_clk) + if(xoff_tx) + pause_time_req <= pause_time; + else if(xon_tx) + pause_time_req <= 0; + + always @(posedge tx_clk) + if(tx_reset) + pause_req <= 0; + else + pause_req <= xon_tx | xoff_tx; -endmodule // flow_ctrl +endmodule // flow_ctrl_rx diff --git a/simple_gemac/simple_gemac.v b/simple_gemac/simple_gemac.v index 5ec2fa2ba..868a66819 100644 --- a/simple_gemac/simple_gemac.v +++ b/simple_gemac/simple_gemac.v @@ -6,7 +6,7 @@ module simple_gemac input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, // Flow Control Interface - input pause_req, input [15:0] pause_time, input pause_en, + input pause_req, input [15:0] pause_time_req, input pause_respect_en, // Settings input [47:0] ucast_addr, input [47:0] mcast_addr, @@ -33,7 +33,7 @@ module simple_gemac .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), .ifg(SGE_IFG), .mac_addr(ucast_addr), - .pause_req(pause_req), .pause_time(pause_time), // We request flow control + .pause_req(pause_req), .pause_time(pause_time_req), // We request flow control .pause_apply(pause_apply), .paused(paused) // We respect flow control ); @@ -50,7 +50,7 @@ module simple_gemac flow_ctrl_tx flow_ctrl_tx (.rst(rst_txclk), .tx_clk(tx_clk), - .tx_pause_en(pause_en), + .tx_pause_en(pause_respect_en), .pause_quanta(pause_quanta_rcvd), // 16 bit value .pause_quanta_val(pause_rcvd), .pause_apply(pause_apply), diff --git a/simple_gemac/simple_gemac_wb.v b/simple_gemac/simple_gemac_wb.v index cc2cdf7ec..6df277e3e 100644 --- a/simple_gemac/simple_gemac_wb.v +++ b/simple_gemac/simple_gemac_wb.v @@ -24,7 +24,9 @@ module simple_gemac_wb inout mdio, output mdc, output [47:0] ucast_addr, output [47:0] mcast_addr, output pass_ucast, output pass_mcast, output pass_bcast, - output pass_pause, output pass_all, output pause_en ); + output pass_pause, output pass_all, + output pause_respect_en, output pause_request_en, + output [15:0] pause_time, output [15:0] pause_thresh ); wire acc = wb_cyc & wb_stb; wire wr_acc = wb_cyc & wb_stb & wb_we; @@ -36,10 +38,10 @@ module simple_gemac_wb else wb_ack <= acc & ~wb_ack; - wire [5:0] misc_settings; - assign {pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en} = misc_settings; + wire [6:0] misc_settings; + assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; - wb_reg #(.ADDR(0),.DEFAULT(6'b111001)) + wb_reg #(.ADDR(0),.DEFAULT(7'b0111001)) wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(misc_settings) ); wb_reg #(.ADDR(1),.DEFAULT(0)) @@ -131,6 +133,14 @@ module simple_gemac_wb .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); + wb_reg #(.ADDR(11),.DEFAULT(0)) + wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(pause_time) ); + + wb_reg #(.ADDR(12),.DEFAULT(0)) + wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(pause_thresh) ); + always @(posedge wb_clk) case(wb_adr[7:2]) 0 : wb_dat_o <= misc_settings; @@ -144,6 +154,8 @@ module simple_gemac_wb 8 : wb_dat_o <= MIICOMMAND; 9 : wb_dat_o <= MIISTATUS; 10: wb_dat_o <= MIIRX_DATA; + 11: wb_dat_o <= pause_time; + 12: wb_dat_o <= pause_thresh; endcase // case (wb_adr[7:2]) endmodule // simple_gemac_wb diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index de445476c..7511f3fb9 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -140,7 +140,12 @@ module simple_gemac_wrapper .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - wire [31:0] debug_tx, debug_rx; + flow_ctrl_rx flow_ctrl_rx + (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh), + .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space), + .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req)); + + wire [31:0] debug_tx, debug_rx; assign debug_tx = { { tx_ll_data }, { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile index 7847b8c72..94681f6cd 100644 --- a/top/u2_rev3/Makefile +++ b/top/u2_rev3/Makefile @@ -90,6 +90,7 @@ simple_gemac/simple_gemac_rx.v \ simple_gemac/crc.v \ simple_gemac/delay_line.v \ simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ simple_gemac/address_filter.v \ simple_gemac/ll8_to_txmac.v \ simple_gemac/rxmac_to_ll8.v \ -- cgit v1.2.3 From fe10969413ff8fff708f4c29ebd05876d059be5a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Sep 2009 22:33:30 -0700 Subject: Untested fixes for getting serdes onto the new fifo system. Compiles, at least --- serdes/serdes_rx.v | 79 +++++++++++---------------------------------------- serdes/serdes_tx.v | 26 ++++++++--------- top/u2_core/u2_core.v | 4 +-- 3 files changed, 30 insertions(+), 79 deletions(-) (limited to 'top') diff --git a/serdes/serdes_rx.v b/serdes/serdes_rx.v index aaca94ff1..afefccaa1 100644 --- a/serdes/serdes_rx.v +++ b/serdes/serdes_rx.v @@ -70,7 +70,7 @@ module serdes_rx reg [31:0] line_i; reg sop_i, eop_i, error_i; - wire error_o, sop_o, eop_o, write, read, empty, full; + wire error_o, sop_o, eop_o, write; reg [15:0] halfline; reg [8:0] holder; wire [31:0] line_o; @@ -82,14 +82,10 @@ module serdes_rx reg write_d; wire rst_rxclk; + wire have_space; + oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk)); - /* - ss_rcvr #(.WIDTH(18)) ss_rcvr - (.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst), - .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(even_data), - .clock_present()); - */ assign even_data = {ser_rkmsb,ser_rklsb,ser_r}; always @(posedge ser_rx_clk) @@ -171,7 +167,7 @@ module serdes_rx if(chosen_data[17:16] == 0) begin line_i <= {chosen_data[15:0],halfline}; - if(full) // No space to write to! Should have been avoided by flow control + if(~have_space) // No space to write to! Should have been avoided by flow control state <= ERROR; else begin @@ -204,7 +200,7 @@ module serdes_rx if(chosen_data[17:16] == 0) begin line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline}; - if(full) // No space to write to! + if(~have_space) // No space to write to! state <= ERROR; else begin @@ -220,7 +216,7 @@ module serdes_rx CRC_CHECK : if(chosen_data[17:0] == {2'b00,CRC}) begin - if(full) + if(~have_space) state <= ERROR; else begin @@ -236,7 +232,7 @@ module serdes_rx ERROR : begin error_i <= 1; - if(~full) + if(have_space) state <= IDLE; end DONE : @@ -263,62 +259,19 @@ module serdes_rx else write_d <= write_pre; // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes - assign write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK)); - - -//`define CASC 1 -`define MYFIFO 1 -//`define XILFIFO 1 + assign write = eop_i | (error_i & have_space) | (write_d & (state != CRC_CHECK)); -`ifdef CASC - cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo - (.clk(clk),.rst(rst),.clear(0), - .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full), - .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty), - .space(fifo_space),.occupied(fifo_occupied) ); - assign fifo_full = full; - assign fifo_empty = empty; -`endif - -`ifdef MYFIFO - wire [FIFOSIZE-1:0] level; - fifo_2clock_casc #(.DWIDTH(35),.AWIDTH(FIFOSIZE)) serdes_rx_fifo + fifo_2clock_cascade #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo (.arst(rst), - .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full), - .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty), - .level_rclk(level) ); - assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - - {{(16-FIFOSIZE){1'b0}},level}; - assign fifo_occupied = { {(16-FIFOSIZE){1'b0}} ,level}; - assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain - assign fifo_empty = empty; -`endif + .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), + .src_rdy_i(write), .dst_rdy_o(have_space), .space(fifo_space), + .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), + .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .occupied(fifo_occupied) ); -`ifdef XILFIFO - wire [FIFOSIZE-1:0] level; - fifo_generator_v4_1 ser_rx_fifo - (.din({error_i,sop_i,eop_i,line_i}), - .rd_clk(clk), - .rd_en(read), - .rst(rst), - .wr_clk(ser_rx_clk), - .wr_en(write), - .dout({error_o,sop_o,eop_o,line_o}), - .empty(empty), - .full(full), - .rd_data_count(level), - .wr_data_count() ); - assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - - {{(16-FIFOSIZE){1'b0}},level}; - assign fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level }; - assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain - assign fifo_empty = empty; -`endif // `ifdef XILFIFO - + assign fifo_full = ~have_space; // Note -- in the wrong clock domain + assign fifo_empty = ~wr_ready_o; // Internal FIFO to Buffer interface - assign read = wr_ready_i & wr_ready_o; - assign wr_ready_o = ~empty; assign wr_dat_o = line_o; assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o }; @@ -334,6 +287,6 @@ module serdes_rx always @(posedge clk) serdes_link_up <= &slu_reg[3:1]; - assign debug = { full, empty, odd, sop_i, eop_i, error_i, state[2:0] }; + assign debug = { have_space, wr_ready_o, odd, sop_i, eop_i, error_i, state[2:0] }; endmodule // serdes_rx diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v index b6f19370e..c74414e92 100644 --- a/serdes/serdes_tx.v +++ b/serdes/serdes_tx.v @@ -77,25 +77,23 @@ module serdes_tx reg [3:0] wait_count; // Internal FIFO, size 9 is 2K, size 10 is 4K bytes - wire sop_o, eop_o, write, full, read, empty; + wire sop_o, eop_o; wire [31:0] data_o; - reg xfer_active; wire rd_sop_i = rd_flags_i[0]; wire rd_eop_i = rd_flags_i[1]; wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused - - cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo - (.clk(clk),.rst(rst),.clear(0), - .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full), - .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty), - .space(), .occupied(fifo_occupied) ); - assign fifo_full = full; - assign fifo_empty = empty; - - assign write = rd_ready_i & rd_ready_o; - assign rd_ready_o = ~full; + wire have_data, empty; + fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo + (.clk(clk),.reset(rst),.clear(0), + .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), + .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data), + .space(), .occupied(fifo_occupied) ); + + assign fifo_full = ~rd_ready_o; + assign empty = ~have_data; + assign fifo_empty = empty; // FIXME Implement flow control reg [15:0] second_word; @@ -182,7 +180,7 @@ module serdes_tx CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC); - assign debug = { 26'd0, full, empty, xfer_active, state[2:0] }; + assign debug = { 28'd0, state[2:0] }; endmodule // serdes_tx diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 918215093..e4c224ab6 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -587,7 +587,7 @@ module u2_core // /////////////////////////////////////////////////////////////////////////////////// // SERDES -/* + serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), @@ -597,7 +597,7 @@ module u2_core .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); -*/ + // /////////////////////////////////////////////////////////////////////////////////// // External RAM Interface -- cgit v1.2.3 From eee63907c03961549eb377ffd933407fb9b9a651 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 5 Sep 2009 13:38:13 -0700 Subject: fix a typo which caused tx glitches --- top/u2_core/u2_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'top') diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 918215093..e55783d0b 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -572,7 +572,7 @@ module u2_core (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_flags_i(rd_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), + .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), .debug(debug_txc) ); -- cgit v1.2.3 From 037332cb6b8618d79e6eb6b20e2a19160e5ace62 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 30 Sep 2009 17:35:14 -0700 Subject: Copied wb_1master back from quad radio more sane config options, should be exactly the same memory map --- control_lib/wb_1master.v | 318 ++++++++++++++++++++++++++--------------------- top/u2_core/u2_core.v | 143 +++++++++------------ 2 files changed, 238 insertions(+), 223 deletions(-) (limited to 'top') diff --git a/control_lib/wb_1master.v b/control_lib/wb_1master.v index e56ba1fb2..fb313efae 100644 --- a/control_lib/wb_1master.v +++ b/control_lib/wb_1master.v @@ -38,26 +38,40 @@ // Up to 8 slaves share a Wishbone Bus connection to 1 master module wb_1master - #(parameter s0_addr_w = 4, // slave 0 address decode width - parameter s0_addr = 4'h0, // slave 0 address - parameter s1_addr_w = 4 , // slave 1 address decode width - parameter s1_addr = 4'h1, // slave 1 address - parameter s215_addr_w = 8 , // slave 2 to slave 7 address decode width - parameter s2_addr = 8'h92, // slave 2 address - parameter s3_addr = 8'h93, // slave 3 address - parameter s4_addr = 8'h94, // slave 4 address - parameter s5_addr = 8'h95, // slave 5 address - parameter s6_addr = 8'h96, // slave 6 address - parameter s7_addr = 8'h97, // slave 7 address - parameter s8_addr = 8'h98, // slave 7 address - parameter s9_addr = 8'h99, // slave 7 address - parameter s10_addr = 8'h9a, // slave 7 address - parameter s11_addr = 8'h9b, // slave 7 address - parameter s12_addr = 8'h9c, // slave 7 address - parameter s13_addr = 8'h9d, // slave 7 address - parameter s14_addr = 8'h9e, // slave 7 address - parameter s15_addr = 8'h9f, // slave 7 address - + #(parameter decode_w = 8, // address decode width + parameter s0_addr = 8'h0, // slave 0 address + parameter s0_mask = 8'h0, // slave 0 don't cares + parameter s1_addr = 8'h0, // slave 1 address + parameter s1_mask = 8'h0, // slave 1 don't cares + parameter s2_addr = 8'h0, // slave 2 address + parameter s2_mask = 8'h0, // slave 2 don't cares + parameter s3_addr = 8'h0, // slave 3 address + parameter s3_mask = 8'h0, // slave 3 don't cares + parameter s4_addr = 8'h0, // slave 4 address + parameter s4_mask = 8'h0, // slave 4 don't cares + parameter s5_addr = 8'h0, // slave 5 address + parameter s5_mask = 8'h0, // slave 5 don't cares + parameter s6_addr = 8'h0, // slave 6 address + parameter s6_mask = 8'h0, // slave 6 don't cares + parameter s7_addr = 8'h0, // slave 7 address + parameter s7_mask = 8'h0, // slave 7 don't cares + parameter s8_addr = 8'h0, // slave 8 address + parameter s8_mask = 8'h0, // slave 8 don't cares + parameter s9_addr = 8'h0, // slave 9 address + parameter s9_mask = 8'h0, // slave 9 don't cares + parameter sa_addr = 8'h0, // slave a address + parameter sa_mask = 8'h0, // slave a don't cares + parameter sb_addr = 8'h0, // slave b address + parameter sb_mask = 8'h0, // slave b don't cares + parameter sc_addr = 8'h0, // slave c address + parameter sc_mask = 8'h0, // slave c don't cares + parameter sd_addr = 8'h0, // slave d address + parameter sd_mask = 8'h0, // slave d don't cares + parameter se_addr = 8'h0, // slave e address + parameter se_mask = 8'h0, // slave e don't cares + parameter sf_addr = 8'h0, // slave f address + parameter sf_mask = 8'h0, // slave f don't cares + parameter dw = 32, // Data bus Width parameter aw = 32, // Address bus Width parameter sw = 4) // Number of Select Lines @@ -188,71 +202,71 @@ input s9_err_i, input s9_rty_i, - input [dw-1:0] s10_dat_i, - output [dw-1:0] s10_dat_o, - output [aw-1:0] s10_adr_o, - output [sw-1:0] s10_sel_o, - output s10_we_o, - output s10_cyc_o, - output s10_stb_o, - input s10_ack_i, - input s10_err_i, - input s10_rty_i, + input [dw-1:0] sa_dat_i, + output [dw-1:0] sa_dat_o, + output [aw-1:0] sa_adr_o, + output [sw-1:0] sa_sel_o, + output sa_we_o, + output sa_cyc_o, + output sa_stb_o, + input sa_ack_i, + input sa_err_i, + input sa_rty_i, - input [dw-1:0] s11_dat_i, - output [dw-1:0] s11_dat_o, - output [aw-1:0] s11_adr_o, - output [sw-1:0] s11_sel_o, - output s11_we_o, - output s11_cyc_o, - output s11_stb_o, - input s11_ack_i, - input s11_err_i, - input s11_rty_i, + input [dw-1:0] sb_dat_i, + output [dw-1:0] sb_dat_o, + output [aw-1:0] sb_adr_o, + output [sw-1:0] sb_sel_o, + output sb_we_o, + output sb_cyc_o, + output sb_stb_o, + input sb_ack_i, + input sb_err_i, + input sb_rty_i, - input [dw-1:0] s12_dat_i, - output [dw-1:0] s12_dat_o, - output [aw-1:0] s12_adr_o, - output [sw-1:0] s12_sel_o, - output s12_we_o, - output s12_cyc_o, - output s12_stb_o, - input s12_ack_i, - input s12_err_i, - input s12_rty_i, + input [dw-1:0] sc_dat_i, + output [dw-1:0] sc_dat_o, + output [aw-1:0] sc_adr_o, + output [sw-1:0] sc_sel_o, + output sc_we_o, + output sc_cyc_o, + output sc_stb_o, + input sc_ack_i, + input sc_err_i, + input sc_rty_i, - input [dw-1:0] s13_dat_i, - output [dw-1:0] s13_dat_o, - output [aw-1:0] s13_adr_o, - output [sw-1:0] s13_sel_o, - output s13_we_o, - output s13_cyc_o, - output s13_stb_o, - input s13_ack_i, - input s13_err_i, - input s13_rty_i, + input [dw-1:0] sd_dat_i, + output [dw-1:0] sd_dat_o, + output [aw-1:0] sd_adr_o, + output [sw-1:0] sd_sel_o, + output sd_we_o, + output sd_cyc_o, + output sd_stb_o, + input sd_ack_i, + input sd_err_i, + input sd_rty_i, - input [dw-1:0] s14_dat_i, - output [dw-1:0] s14_dat_o, - output [aw-1:0] s14_adr_o, - output [sw-1:0] s14_sel_o, - output s14_we_o, - output s14_cyc_o, - output s14_stb_o, - input s14_ack_i, - input s14_err_i, - input s14_rty_i, + input [dw-1:0] se_dat_i, + output [dw-1:0] se_dat_o, + output [aw-1:0] se_adr_o, + output [sw-1:0] se_sel_o, + output se_we_o, + output se_cyc_o, + output se_stb_o, + input se_ack_i, + input se_err_i, + input se_rty_i, - input [dw-1:0] s15_dat_i, - output [dw-1:0] s15_dat_o, - output [aw-1:0] s15_adr_o, - output [sw-1:0] s15_sel_o, - output s15_we_o, - output s15_cyc_o, - output s15_stb_o, - input s15_ack_i, - input s15_err_i, - input s15_rty_i + input [dw-1:0] sf_dat_i, + output [dw-1:0] sf_dat_o, + output [aw-1:0] sf_adr_o, + output [sw-1:0] sf_sel_o, + output sf_we_o, + output sf_cyc_o, + output sf_stb_o, + input sf_ack_i, + input sf_err_i, + input sf_rty_i ); // //////////////////////////////////////////////////////////////// @@ -278,22 +292,22 @@ 128 : i_dat_s <= s7_dat_i; 256 : i_dat_s <= s8_dat_i; 512 : i_dat_s <= s9_dat_i; - 1024 : i_dat_s <= s10_dat_i; - 2048 : i_dat_s <= s11_dat_i; - 4096 : i_dat_s <= s12_dat_i; - 8192 : i_dat_s <= s13_dat_i; - 16384 : i_dat_s <= s14_dat_i; - 32768 : i_dat_s <= s15_dat_i; + 1024 : i_dat_s <= sa_dat_i; + 2048 : i_dat_s <= sb_dat_i; + 4096 : i_dat_s <= sc_dat_i; + 8192 : i_dat_s <= sd_dat_i; + 16384 : i_dat_s <= se_dat_i; + 32768 : i_dat_s <= sf_dat_i; default : i_dat_s <= s0_dat_i; endcase // case(ssel_dec) assign {m0_ack_o, m0_err_o, m0_rty_o} = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i | - s8_ack_i | s9_ack_i | s10_ack_i | s11_ack_i | s12_ack_i | s13_ack_i | s14_ack_i | s15_ack_i , + s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i , s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | - s8_err_i | s9_err_i | s10_err_i | s11_err_i | s12_err_i | s13_err_i | s14_err_i | s15_err_i , + s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i , s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i | - s8_rty_i | s9_rty_i | s10_rty_i | s11_rty_i | s12_rty_i | s13_rty_i | s14_rty_i | s15_rty_i }; + s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i }; // Slave output interfaces assign s0_adr_o = m0_adr_i; @@ -366,65 +380,85 @@ assign s9_cyc_o = m0_cyc_i; assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9]; - assign s10_adr_o = m0_adr_i; - assign s10_sel_o = m0_sel_i; - assign s10_dat_o = m0_dat_i; - assign s10_we_o = m0_we_i; - assign s10_cyc_o = m0_cyc_i; - assign s10_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10]; + assign sa_adr_o = m0_adr_i; + assign sa_sel_o = m0_sel_i; + assign sa_dat_o = m0_dat_i; + assign sa_we_o = m0_we_i; + assign sa_cyc_o = m0_cyc_i; + assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10]; - assign s11_adr_o = m0_adr_i; - assign s11_sel_o = m0_sel_i; - assign s11_dat_o = m0_dat_i; - assign s11_we_o = m0_we_i; - assign s11_cyc_o = m0_cyc_i; - assign s11_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11]; + assign sb_adr_o = m0_adr_i; + assign sb_sel_o = m0_sel_i; + assign sb_dat_o = m0_dat_i; + assign sb_we_o = m0_we_i; + assign sb_cyc_o = m0_cyc_i; + assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11]; - assign s12_adr_o = m0_adr_i; - assign s12_sel_o = m0_sel_i; - assign s12_dat_o = m0_dat_i; - assign s12_we_o = m0_we_i; - assign s12_cyc_o = m0_cyc_i; - assign s12_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12]; + assign sc_adr_o = m0_adr_i; + assign sc_sel_o = m0_sel_i; + assign sc_dat_o = m0_dat_i; + assign sc_we_o = m0_we_i; + assign sc_cyc_o = m0_cyc_i; + assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12]; - assign s13_adr_o = m0_adr_i; - assign s13_sel_o = m0_sel_i; - assign s13_dat_o = m0_dat_i; - assign s13_we_o = m0_we_i; - assign s13_cyc_o = m0_cyc_i; - assign s13_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13]; + assign sd_adr_o = m0_adr_i; + assign sd_sel_o = m0_sel_i; + assign sd_dat_o = m0_dat_i; + assign sd_we_o = m0_we_i; + assign sd_cyc_o = m0_cyc_i; + assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13]; - assign s14_adr_o = m0_adr_i; - assign s14_sel_o = m0_sel_i; - assign s14_dat_o = m0_dat_i; - assign s14_we_o = m0_we_i; - assign s14_cyc_o = m0_cyc_i; - assign s14_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14]; + assign se_adr_o = m0_adr_i; + assign se_sel_o = m0_sel_i; + assign se_dat_o = m0_dat_i; + assign se_we_o = m0_we_i; + assign se_cyc_o = m0_cyc_i; + assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14]; - assign s15_adr_o = m0_adr_i; - assign s15_sel_o = m0_sel_i; - assign s15_dat_o = m0_dat_i; - assign s15_we_o = m0_we_i; - assign s15_cyc_o = m0_cyc_i; - assign s15_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15]; + assign sf_adr_o = m0_adr_i; + assign sf_sel_o = m0_sel_i; + assign sf_dat_o = m0_dat_i; + assign sf_we_o = m0_we_i; + assign sf_cyc_o = m0_cyc_i; + assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15]; // Address decode logic // WARNING -- must make sure these are mutually exclusive! - assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); - assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); - assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s2_addr); - assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s3_addr); - assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s4_addr); - assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s5_addr); - assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s6_addr); - assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s7_addr); - assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s8_addr); - assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s9_addr); - assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s10_addr); - assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s11_addr); - assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s12_addr); - assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s13_addr); - assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s14_addr); - assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s15_addr); - + + + assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask); + assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask); + assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask); + assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask); + assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask); + assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask); + assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask); + assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask); + assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask); + assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask); + assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask); + assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask); + assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask); + assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask); + assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask); + assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask); + +/* + assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr); + assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr); + assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr); + assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr); + assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr); + assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr); + assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr); + assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr); + assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr); + assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr); + assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr); + assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr); + assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr); + assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr); + assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr); + assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr); + */ endmodule // wb_1master diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index f12b5af4d..5718366d5 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -168,57 +168,68 @@ module u2_core wire [dw-1:0] m0_dat_o, m0_dat_i; wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, - s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; - wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; - wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; - - wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), - .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), - .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), - .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), - .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), - .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), - .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), - .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), - .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), - .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), - .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), - .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), - .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), - .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), - .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), - .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); ////////////////////////////////////////////////////////////////////////////////////////// // Reset Controller @@ -300,9 +311,6 @@ module u2_core .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), .flush_icache(flush_icache)); - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(flush_icache)); @@ -322,7 +330,7 @@ module u2_core buffer_pool buffer_pool (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), .stream_clk(dsp_clk), .stream_rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), @@ -355,12 +363,10 @@ module u2_core spi_top shared_spi (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - assign s2_rty = 1'b0; - // I2C -- Slave #3 i2c_master_top #(.ARST_LVL(1)) i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), @@ -371,8 +377,6 @@ module u2_core .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); assign s3_dat_i[31:8] = 24'd0; - assign s3_err = 1'b0; - assign s3_rty = 1'b0; // GPIOs -- Slave #4 nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), @@ -380,8 +384,6 @@ module u2_core .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); - assign s4_err = 1'b0; - assign s4_rty = 1'b0; // Buffer Pool Status -- Slave #5 wb_readback_mux buff_pool_status @@ -398,9 +400,6 @@ module u2_core .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) ); - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - // Slave, #6 Ethernet MAC, see below // Settings Bus -- Slave #7 @@ -409,8 +408,6 @@ module u2_core .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - assign s7_err = 1'b0; - assign s7_rty = 1'b0; assign s7_dat_i = 32'd0; // Output control lines @@ -476,9 +473,6 @@ module u2_core .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), .debug0(debug_mac0),.debug1(debug_mac1) ); - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - mac_rxfifo_int mac_rxfifo_int (.clk(dsp_clk),.rst(dsp_rst), .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), @@ -506,8 +500,6 @@ module u2_core (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), .irq(irq) ); - assign s8_err = 0; - assign s8_rty = 0; // ///////////////////////////////////////////////////////////////////////// // Master Timer, Slave #9 @@ -518,22 +510,17 @@ module u2_core .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - assign s9_err = 0; - assign s9_rty = 0; // ///////////////////////////////////////////////////////////////////////// // UART, Slave #10 simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), - .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - assign s10_err = 0; - assign s10_rty = 0; - // ///////////////////////////////////////////////////////////////////////// // ATR Controller, Slave #11 @@ -544,11 +531,9 @@ module u2_core atr_controller atr_controller (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), - .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - assign s11_err = 0; - assign s11_rty = 0; // ////////////////////////////////////////////////////////////////////////// // Time Sync, Slave #12 @@ -562,14 +547,12 @@ module u2_core wire pps_o; time_sync time_sync (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), - .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), + .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), + .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), .sys_clk_i(dsp_clk),.master_time_o(master_time), .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - assign s12_err = 0; - assign s12_rty = 0; // ///////////////////////////////////////////////////////////////////////// // SD Card Reader / Writer, Slave #13 @@ -577,11 +560,10 @@ module u2_core sd_spi_wb sd_spi_wb (.clk(wb_clk),.rst(wb_rst), .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we), - .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i), - .wb_ack_o(s13_ack) ); - assign s13_err = 0; - assign s13_rty = 0; + .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i), + .wb_ack_o(sd_ack) ); + // ///////////////////////////////////////////////////////////////////////// // DSP wire [31:0] sample_rx, sample_tx; @@ -655,8 +637,8 @@ module u2_core wb_bridge_16_32 bridge (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), - .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), + .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), + .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); @@ -668,7 +650,6 @@ module u2_core .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), .sram_mode(),.sram_zz() ); - assign s14_err = 0; assign s14_rty = 0; assign RAM_CE1n = 0; assign RAM_D[17:16] = 2'bzz; -- cgit v1.2.3 From 50b1decab6903ec2053995ebc696f7ade37f9537 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 30 Sep 2009 18:37:47 -0700 Subject: no idea where this came from, it shouldn't be here --- top/u2_core/u2_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'top') diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 456800521..363f7340e 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -510,7 +510,7 @@ module u2_core (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.master_time(), .ctrl_lines(atr_lines) ); + .run_rx(run_rx_d1),.run_tx(run_tx), .ctrl_lines(atr_lines) ); assign s11_err = 0; assign s11_rty = 0; -- cgit v1.2.3 From 0a0655b56b84aa6557cdfaece206d0f5cf6ebeac Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Oct 2009 00:21:24 -0700 Subject: fullchip sim now compiles again, after moving eth and models over to new simple_gemac --- models/miim_model.v | 14 +++++ models/phy_sim.v | 113 ++++++++++++++++++++++++++++++++++++++ models/xlnx_glbl.v | 29 ++++++++++ testbench/cmdfile | 18 +----- top/single_u2_sim/single_u2_sim.v | 2 +- 5 files changed, 159 insertions(+), 17 deletions(-) create mode 100644 models/miim_model.v create mode 100644 models/phy_sim.v create mode 100644 models/xlnx_glbl.v (limited to 'top') diff --git a/models/miim_model.v b/models/miim_model.v new file mode 100644 index 000000000..936d99a80 --- /dev/null +++ b/models/miim_model.v @@ -0,0 +1,14 @@ + +// Skeleton PHY interface simulator + +module miim_model(input mdc_i, + inout mdio, + input phy_resetn_i, + input phy_clk_i, + output phy_intn_o, + output [2:0] speed_o); + + assign phy_intn_o = 1; // No interrupts + assign speed_o = 3'b100; // 1G mode + +endmodule // miim_model diff --git a/models/phy_sim.v b/models/phy_sim.v new file mode 100644 index 000000000..b3de19b04 --- /dev/null +++ b/models/phy_sim.v @@ -0,0 +1,113 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_sim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Phy_sim.v,v $ +// Revision 1.3 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.2 2006/01/19 14:07:50 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +`timescale 1ns/100ps + +module phy_sim( + input Gtx_clk, // Used only in GMII mode + output Rx_clk, + output Tx_clk, // Used only in MII mode + input Tx_er, + input Tx_en, + input [7:0] Txd, + output Rx_er, + output Rx_dv, + output [7:0] Rxd, + output Crs, + output Col, + input [2:0] Speed, + input Done +); + +////////////////////////////////////////////////////////////////////// +// this file used to simulate Phy. +// generate clk and loop the Tx data to Rx data +// full duplex mode can be verified on loop mode. +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +// internal signals +////////////////////////////////////////////////////////////////////// +reg Clk_25m; // Used for 100 Mbps mode +reg Clk_2_5m; // Used for 10 Mbps mode + +//wire Rx_clk; +//wire Tx_clk; // Used only in MII mode + + initial + begin + #10; + while ( !Done ) + begin + #20 Clk_25m = 0; + #20 Clk_25m = 1; + end + end + + initial + begin + #10; + while ( !Done ) + begin + #200 Clk_2_5m = 0; + #200 Clk_2_5m = 1; + end + end + + assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; + assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; + + assign Rx_dv = Tx_en; + assign Rxd = Txd; + assign Rx_er = Tx_er; + assign Crs = Tx_en; + assign Col = 0; + +endmodule diff --git a/models/xlnx_glbl.v b/models/xlnx_glbl.v new file mode 100644 index 000000000..662a60e35 --- /dev/null +++ b/models/xlnx_glbl.v @@ -0,0 +1,29 @@ +module xlnx_glbl +( + GSR, + GTS +); + + //-------------------------------------------------------------------------- + // Parameters + //-------------------------------------------------------------------------- + + //-------------------------------------------------------------------------- + // IO declarations + //-------------------------------------------------------------------------- + + output GSR; + output GTS; + + //-------------------------------------------------------------------------- + // Local declarations + //-------------------------------------------------------------------------- + + //-------------------------------------------------------------------------- + // Internal declarations + //-------------------------------------------------------------------------- + + assign GSR = 0; + assign GTS = 0; + +endmodule diff --git a/testbench/cmdfile b/testbench/cmdfile index ed251665c..8083eb92a 100644 --- a/testbench/cmdfile +++ b/testbench/cmdfile @@ -9,6 +9,8 @@ -y ../timing -y ../coregen -y ../extram +-y ../simple_gemac +-y ../simple_gemac/miim # Models -y ../models @@ -18,24 +20,8 @@ -y ../opencores/8b10b -y ../opencores/spi/rtl/verilog +incdir+../opencores/spi/rtl/verilog --y ../opencores/wb_conbus/rtl/verilog -+incdir+../opencores/wb_conbus/rtl/verilog -y ../opencores/i2c/rtl/verilog +incdir+../opencores/i2c/rtl/verilog -y ../opencores/aemb/rtl/verilog -y ../opencores/simple_pic/rtl -# Ethernet -+incdir+../eth/rtl/verilog --y ../eth/rtl/verilog --y ../eth/rtl/verilog/MAC_tx --y ../eth/rtl/verilog/MAC_rx --y ../eth/rtl/verilog/miim --y ../eth/rtl/verilog/TECH --y ../eth/rtl/verilog/TECH/xilinx --y ../eth/rtl/verilog/RMON --y ../eth --y ../eth/bench/verilog - -# Ethernet Models --y ../eth/bench/verilog diff --git a/top/single_u2_sim/single_u2_sim.v b/top/single_u2_sim/single_u2_sim.v index 016815ff7..2a7b24849 100644 --- a/top/single_u2_sim/single_u2_sim.v +++ b/top/single_u2_sim/single_u2_sim.v @@ -178,7 +178,7 @@ module single_u2_sim(); .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); wire [2:0] speed; - Phy_sim phy_model + phy_sim phy_model (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), -- cgit v1.2.3 From 42fc55415af499980901c7787f44c7e74b4a9ce1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Oct 2009 01:02:25 -0700 Subject: Fix warnings, mostly from implicitly defined wires or unspecified widths --- serdes/serdes_tx.v | 2 +- simple_gemac/flow_ctrl_rx.v | 1 + simple_gemac/simple_gemac.v | 3 ++- simple_gemac/simple_gemac_rx.v | 2 +- simple_gemac/simple_gemac_wrapper.v | 10 ++++++---- top/u2_core/u2_core.v | 4 +++- 6 files changed, 14 insertions(+), 8 deletions(-) (limited to 'top') diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v index c74414e92..2e5e3bd80 100644 --- a/serdes/serdes_tx.v +++ b/serdes/serdes_tx.v @@ -84,7 +84,7 @@ module serdes_tx wire rd_eop_i = rd_flags_i[1]; wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused - wire have_data, empty; + wire have_data, empty, read; fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo (.clk(clk),.reset(rst),.clear(0), .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), diff --git a/simple_gemac/flow_ctrl_rx.v b/simple_gemac/flow_ctrl_rx.v index b13334d0e..d09bf377f 100644 --- a/simple_gemac/flow_ctrl_rx.v +++ b/simple_gemac/flow_ctrl_rx.v @@ -42,6 +42,7 @@ module flow_ctrl_rx countdown <= countdown - 1; // Cross clock domains + wire xon_tx, xoff_tx; oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx)); oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx)); diff --git a/simple_gemac/simple_gemac.v b/simple_gemac/simple_gemac.v index 868a66819..e7f327358 100644 --- a/simple_gemac/simple_gemac.v +++ b/simple_gemac/simple_gemac.v @@ -26,7 +26,8 @@ module simple_gemac reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk)); wire [15:0] pause_quanta_rcvd; - + wire pause_rcvd, pause_apply, paused; + simple_gemac_tx simple_gemac_tx (.clk125(clk125),.reset(rst_txclk), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), diff --git a/simple_gemac/simple_gemac_rx.v b/simple_gemac/simple_gemac_rx.v index bad43a607..45ddd6dfa 100644 --- a/simple_gemac/simple_gemac_rx.v +++ b/simple_gemac/simple_gemac_rx.v @@ -47,7 +47,7 @@ module simple_gemac_rx localparam DELAY = 6; delay_line #(.WIDTH(10)) rx_delay - (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_dl,rxd_del})); + (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del})); always @(posedge rx_clk) if(reset) diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index 71ad0cf0f..efcf89276 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -19,13 +19,15 @@ module simple_gemac_wrapper // MIIM inout mdio, output mdc, output [31:0] debug); - + + wire clear = 0; wire [7:0] rx_data, tx_data; wire tx_clk, tx_valid, tx_error, tx_ack; wire rx_clk, rx_valid, rx_error, rx_ack; wire [47:0] ucast_addr, mcast_addr; wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; + wire pause_req; wire pause_request_en, pause_respect_en; wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; @@ -75,15 +77,15 @@ module simple_gemac_wrapper rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), + .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); ll8_shortfifo rx_sfifo (.clk(rx_clk), .reset(rx_reset), .clear(0), .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), + .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); + .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2; diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 1f78f6d3d..03016e9b3 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -525,9 +525,11 @@ module u2_core (.clk(wb_clk),.rst(wb_rst), .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), .wb_ack_o(sd_ack) ); + assign sd_dat_i[31:8] = 0; + // ///////////////////////////////////////////////////////////////////////// // DSP wire [31:0] sample_rx, sample_tx; -- cgit v1.2.3