From 7ffbd04c273ef96472e18f98a40b3ad171bc0c9b Mon Sep 17 00:00:00 2001 From: jcorgan Date: Thu, 30 Jul 2009 21:54:38 +0000 Subject: Add custom FPGA build. This is a custom build for USRP2 FPGA. It allows using a BasicRX or LFRX board and feed two independent, real signals. In addition, instead of the CIC/HB decimator, which optimizes frequency response, it uses an integrate and dump decimator, which optimizes for time-domain impulse response. These changes have been made in dsp_core_rx.v: * A second DDC has been added, sharing a frequency register with the existing DDC. * The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... into the receive FIFO. This limits the host configured decimation to 8 intead of 4. Use gr.deinterleave to recover the streams. * The ADCs are hardcoded: RX_A ==> DDC #1 I-input 0 ==> DDC #1 Q-input RX_B ==> DDC #2 I-input 0 ==> DDC #2 Q-input Thus, the input mux has been disabled. * The CIC/HB decimator has been replaced by an integrate and dump at the decimation rate. * To assist with meeting timing, the external RAM has been disabled. The basic application is to coherently sample two real IF streams and downconvert to baseband, while minimizing the impulse response duration of the resampling filters. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11519 221aa14e-8319-0410-a670-987f0aec2ac5 --- top/u2_rev3_iad/Makefile | 4 ++-- top/u2_rev3_iad/impulse.v | 2 +- top/u2_rev3_iad/integrate.v | 38 -------------------------------------- 3 files changed, 3 insertions(+), 41 deletions(-) delete mode 100644 top/u2_rev3_iad/integrate.v (limited to 'top/u2_rev3_iad') diff --git a/top/u2_rev3_iad/Makefile b/top/u2_rev3_iad/Makefile index 24dffd92b..5ae8846dd 100644 --- a/top/u2_rev3_iad/Makefile +++ b/top/u2_rev3_iad/Makefile @@ -159,6 +159,7 @@ sdr_lib/cordic_stage.v \ sdr_lib/dsp_core_tx.v \ sdr_lib/hb_dec.v \ sdr_lib/hb_interp.v \ +sdr_lib/integrate.v \ sdr_lib/round.v \ sdr_lib/round_reg.v \ sdr_lib/rx_control.v \ @@ -179,8 +180,7 @@ timing/timer.v \ top/u2_core/u2_core.v \ top/u2_rev3/u2_rev3.ucf \ top/u2_rev3/u2_rev3.v \ -top/u2_rev3_iad/dsp_core_rx.v \ -top/u2_rev3_iad/integrate.v +top/u2_rev3_iad/dsp_core_rx.v ################################################## # Process Properties diff --git a/top/u2_rev3_iad/impulse.v b/top/u2_rev3_iad/impulse.v index ecdf101ab..7f0cdc9be 100644 --- a/top/u2_rev3_iad/impulse.v +++ b/top/u2_rev3_iad/impulse.v @@ -60,4 +60,4 @@ module impulse assign adc_ovf_a = 0; assign adc_ovf_b = 0; -endmodule // adc_model +endmodule // impulse diff --git a/top/u2_rev3_iad/integrate.v b/top/u2_rev3_iad/integrate.v deleted file mode 100644 index db33de979..000000000 --- a/top/u2_rev3_iad/integrate.v +++ /dev/null @@ -1,38 +0,0 @@ -module integrate - #(parameter INPUTW = 16, - parameter ACCUMW = 32, - parameter OUTPUTW = 16) - - (input clk_i, - input rst_i, - input ena_i, - - input dump_i, - input [INPUTW-1:0] data_i, - - output reg stb_o, - output reg [OUTPUTW-1:0] integ_o - ); - - wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i}; - reg [ACCUMW-1:0] accum; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - begin - accum <= 0; - integ_o <= 0; - end - else - if (dump_i) - begin - integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW]; - accum <= data_ext; - end - else - accum <= accum + data_ext; - - always @(posedge clk_i) - stb_o <= dump_i; - -endmodule // integrate -- cgit v1.2.3