From a2dda5e9cffe5ceab925175aaaf7c35a52a45a43 Mon Sep 17 00:00:00 2001 From: matt Date: Wed, 22 Oct 2008 00:29:15 +0000 Subject: make rev2 compile again git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9815 221aa14e-8319-0410-a670-987f0aec2ac5 --- top/u2_rev2/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'top/u2_rev2') diff --git a/top/u2_rev2/Makefile b/top/u2_rev2/Makefile index 84243baf8..22aaeafe2 100644 --- a/top/u2_rev2/Makefile +++ b/top/u2_rev2/Makefile @@ -62,7 +62,6 @@ control_lib/cascadefifo2.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ control_lib/dpram32.v \ -control_lib/extram_interface.v \ control_lib/fifo_2clock.v \ control_lib/fifo_2clock_casc.v \ control_lib/gray2bin.v \ @@ -89,6 +88,7 @@ control_lib/simple_uart_rx.v \ control_lib/oneshot_2clk.v \ control_lib/sd_spi.v \ control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ coregen/fifo_xlnx_2Kx36_2clk.v \ coregen/fifo_xlnx_2Kx36_2clk.xco \ coregen/fifo_xlnx_512x36_2clk.v \ @@ -120,6 +120,7 @@ eth/rtl/verilog/flow_ctrl_tx.v \ eth/rtl/verilog/miim/eth_clockgen.v \ eth/rtl/verilog/miim/eth_outputcontrol.v \ eth/rtl/verilog/miim/eth_shiftreg.v \ +extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -- cgit v1.2.3