From 91636cbac2b3edfba45321f1050d0b90b34ab696 Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Mon, 31 Aug 2009 12:08:30 -0700 Subject: Merged SVN matt/new_eth r10782:11633 into new_eth * svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz. --- simple_gemac/simple_gemac_wrapper.v | 65 ++++++++++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 8 deletions(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index cd586ae5d..e21eafb80 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -8,13 +8,10 @@ module simple_gemac_wrapper // Flow Control Interface input pause_req, input [15:0] pause_time, - // RX Client Interface - output rx_clk, output [7:0] rx_ll_data, output rx_ll_sof, output rx_ll_eof, - output rx_ll_error, output rx_ll_src_rdy, input rx_ll_dst_rdy, - - // TX Client Interface - output tx_clk, input [7:0] tx_ll_data, input tx_ll_sof, input tx_ll_eof, - input tx_ll_src_rdy, output tx_ll_dst_rdy, + // Client FIFO Interfaces + input sys_clk, + output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, + input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, // Wishbone Interface input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, @@ -59,14 +56,66 @@ module simple_gemac_wrapper .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), .pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) ); + // RX FIFO Chain + wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2_n, rx_ll_dst_rdy2; + wire [7:0] rx_ll_data, rx_ll_data2; + wire [35:0] rx_f36_data_int1; + wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; + rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); + + ll8_shortfifo rx_sfifo + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), + .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), + .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), + .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(~rx_ll_dst_rdy2_n)); + + ll8_to_fifo36 ll8_to_fifo36 + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2), + .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), + .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1)); + + cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) rx_2clk_fifo + (.wclk(rx_clk), .datain(rx_f36_data_int1), + .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .level_wclk(), + .rclk(sys_clk), .dataout(rx_f36_data), + .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .level_rclk(), .arst(reset)); + + // TX FIFO Chain + wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; + wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; + wire [7:0] tx_ll_data, tx_ll_data2; + wire [35:0] tx_f36_data_int1; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + + cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) tx_2clk_fifo + (.wclk(sys_clk), .datain(tx_f36_data), + .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .level_wclk(), + .rclk(tx_clk), .dataout(tx_f36_data_int1), + .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .level_rclk(), .arst(reset)); + + fifo36_to_ll8 fifo36_to_ll8 + (.clk(tx_clk), .reset(tx_reset), .clear(clear), + .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), + .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), + .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2)); + + ll8_shortfifo tx_sfifo + (.clk(rx_clk), .reset(tx_reset), .clear(clear), + .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), + .error_i(0), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2), + .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), + .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); ll8_to_txmac ll8_to_txmac - (.clk(tx_clk), .reset(tx_reset), .clear(0), + (.clk(tx_clk), .reset(tx_reset), .clear(clear), .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); -- cgit v1.2.3 From f4e4c9b99d753e477fe4151609767ef4245efd4a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 2 Sep 2009 17:01:28 -0700 Subject: sort out active-low lines on locallink fifos, added debug pins --- simple_gemac/simple_gemac_wrapper.v | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index e21eafb80..31bc02ebb 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -18,7 +18,8 @@ module simple_gemac_wrapper input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, // MIIM - inout mdio, output mdc ); + inout mdio, output mdc, + output [31:0] debug); wire [7:0] rx_data, tx_data; wire tx_clk, tx_valid, tx_error, tx_ack; @@ -91,6 +92,7 @@ module simple_gemac_wrapper // TX FIFO Chain wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; + wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; wire [7:0] tx_ll_data, tx_ll_data2; wire [35:0] tx_f36_data_int1; wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; @@ -105,12 +107,17 @@ module simple_gemac_wrapper (.clk(tx_clk), .reset(tx_reset), .clear(clear), .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), - .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2)); + .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n)); + + assign tx_ll_sof2 = ~tx_ll_sof2_n; + assign tx_ll_eof2 = ~tx_ll_eof2_n; + assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n; + assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2; ll8_shortfifo tx_sfifo (.clk(rx_clk), .reset(tx_reset), .clear(clear), .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), - .error_i(0), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2), + .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); @@ -120,4 +127,9 @@ module simple_gemac_wrapper .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); + assign debug = { { tx_ll_data }, + { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, + tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, + { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, + { tx_data} }; endmodule // simple_gemac_wrapper -- cgit v1.2.3 From 5ce99ee61bad4f9c421a873aa2f3144e8e2aebe7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 3 Sep 2009 14:13:44 -0700 Subject: MAC transmit seems to work now. The root cause of the problem was accidentally using the rx_clk in one stage of the fifos on the tx side. --- control_lib/newfifo/fifo_2clock.v | 33 ++++++++++++++------ simple_gemac/simple_gemac_wrapper.v | 31 ++++++++++++------- simple_gemac/simple_gemac_wrapper_tb.v | 17 ++++++----- top/u2_rev3/Makefile | 56 +++++++++++----------------------- 4 files changed, 70 insertions(+), 67 deletions(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v index 40c479db7..2ada39fb0 100644 --- a/control_lib/newfifo/fifo_2clock.v +++ b/control_lib/newfifo/fifo_2clock.v @@ -2,26 +2,39 @@ // FIXME ignores the AWIDTH (fifo size) parameter module fifo_2clock - #(parameter WIDTH=32, SIZE=9) + #(parameter WIDTH=36, SIZE=6) (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input arst); - wire [SIZE-1:0] level_rclk, level_wclk; - wire full, empty, write, read; + wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels + wire full, empty, write, read; assign dst_rdy_o = ~full; assign src_rdy_o = ~empty; assign write = src_rdy_i & dst_rdy_o; assign read = src_rdy_o & dst_rdy_i; - - fifo_xlnx_512x36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - assign occupied = {{(16-SIZE){1'b0}},level_rclk}; - assign space = ((1< Date: Fri, 4 Sep 2009 16:43:11 -0700 Subject: allow control of whether or not to honor flow control, adds some debug lines --- simple_gemac/simple_gemac_wrapper.v | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index b9bc05848..8da77f096 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -38,7 +38,7 @@ module simple_gemac_wrapper .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .pause_en(1), + .pause_req(pause_req), .pause_time(pause_time), .pause_en(pause_en), .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), .pass_pause(pass_pause), .pass_all(pass_all), @@ -136,9 +136,19 @@ module simple_gemac_wrapper .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - assign debug = { { tx_ll_data }, - { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, - tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, - { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, - { tx_data} }; + wire [31:0] debug_tx, debug_rx; + + assign debug_tx = { { tx_ll_data }, + { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, + tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, + { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, + { tx_data} }; + assign debug_rx = { { rx_ll_data }, + { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, + rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, + { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]}, + { rx_data} }; + + assign debug = debug_rx; + endmodule // simple_gemac_wrapper -- cgit v1.2.3 From 71babf966d8cd340eb62122a297c2cc3b1294b82 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Sep 2009 22:20:19 -0700 Subject: parameterized fifo sizes, some reformatting --- simple_gemac/simple_gemac_wrapper.v | 106 +++++++++++++++++++----------------- top/u2_core/u2_core.v | 5 +- 2 files changed, 57 insertions(+), 54 deletions(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index 8da77f096..de445476c 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -1,44 +1,46 @@ module simple_gemac_wrapper - (input clk125, input reset, - // GMII - output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, - input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, - - // Flow Control Interface - input pause_req, input [15:0] pause_time, - - // Client FIFO Interfaces - input sys_clk, - output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, - input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, - - // Wishbone Interface - input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, - input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, - - // MIIM - inout mdio, output mdc, - output [31:0] debug); - - wire [7:0] rx_data, tx_data; - wire tx_clk, tx_valid, tx_error, tx_ack; - wire rx_clk, rx_valid, rx_error, rx_ack; - - wire [47:0] ucast_addr, mcast_addr; - wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en; - - wire rst_rxclk, rst_txclk; + #(parameter RXFIFOSIZE=9, + parameter TXFIFOSIZE=6) + (input clk125, input reset, + // GMII + output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, + input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, + + // Client FIFO Interfaces + input sys_clk, + output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy, + input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy, + + // Wishbone Interface + input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we, + input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o, + + // MIIM + inout mdio, output mdc, + output [31:0] debug); + + wire [7:0] rx_data, tx_data; + wire tx_clk, tx_valid, tx_error, tx_ack; + wire rx_clk, rx_valid, rx_error, rx_ack; + + wire [47:0] ucast_addr, mcast_addr; + wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; + wire pause_request_en, pause_respect_en; + wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; + + wire tx_reset, rx_reset; reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset)); reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset)); - + simple_gemac simple_gemac (.clk125(clk125), .reset(reset), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .pause_en(pause_en), + .pause_req(pause_req), .pause_time_req(pause_time_req), + .pause_respect_en(pause_respect_en), .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), .pass_pause(pass_pause), .pass_all(pass_all), @@ -55,18 +57,20 @@ module simple_gemac_wrapper .mdio(mdio), .mdc(mdc), .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), - .pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) ); + .pass_pause(pass_pause), .pass_all(pass_all), + .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en), + .pause_time(pause_time), .pause_thresh(pause_thresh) ); // RX FIFO Chain - wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; - wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; - - wire [7:0] rx_ll_data, rx_ll_data2; - - wire [35:0] rx_f36_data_int1; - wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; + wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + + wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; + wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; + + wire [7:0] rx_ll_data, rx_ll_data2; + + wire [35:0] rx_f36_data_int1; + wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), @@ -92,21 +96,21 @@ module simple_gemac_wrapper .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1)); - fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) rx_2clk_fifo + fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo (.wclk(rx_clk), .datain(rx_f36_data_int1), - .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(), + .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space), .rclk(sys_clk), .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset)); // TX FIFO Chain - wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; - wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; - wire [7:0] tx_ll_data, tx_ll_data2; - wire [35:0] tx_f36_data_int1; - wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; - - fifo_2clock #(.WIDTH(36), .SIZE(6)) tx_2clk_fifo + wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; + wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; + wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; + wire [7:0] tx_ll_data, tx_ll_data2; + wire [35:0] tx_f36_data_int1; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + + fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index cd0800afc..918215093 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -398,13 +398,12 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - simple_gemac_wrapper simple_gemac_wrapper + simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(0), .pause_time(0), .sys_clk(dsp_clk), .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), @@ -676,7 +675,7 @@ module u2_core { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; */ assign debug = { { GMII_RXD }, - { 1'd0, debug_mac2[3:0], GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, { wr2_flags, rd2_flags }, { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; -- cgit v1.2.3 From c21464b1107295575afa958e34f915f7d9985c14 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Sep 2009 22:23:27 -0700 Subject: Implement Eth flow control using pause frames Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though. --- simple_gemac/flow_ctrl_rx.v | 105 ++++++++++++++---------------------- simple_gemac/simple_gemac.v | 6 +-- simple_gemac/simple_gemac_wb.v | 20 +++++-- simple_gemac/simple_gemac_wrapper.v | 7 ++- top/u2_rev3/Makefile | 1 + 5 files changed, 66 insertions(+), 73 deletions(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/simple_gemac/flow_ctrl_rx.v b/simple_gemac/flow_ctrl_rx.v index 7ded9e08b..b13334d0e 100644 --- a/simple_gemac/flow_ctrl_rx.v +++ b/simple_gemac/flow_ctrl_rx.v @@ -2,84 +2,59 @@ // RX side of flow control -- when we are running out of RX space, send a PAUSE module flow_ctrl_rx - (input rst, - //host processor - input pause_frame_send_en, - input [15:0] pause_quanta_set, - input [15:0] fc_hwmark, - input [15:0] fc_lwmark, - // From MAC_rx_ctrl - input rx_clk, - input [15:0] rx_fifo_space, - // MAC_tx_ctrl - input tx_clk, - output reg xoff_gen, - output reg xon_gen, - input xoff_gen_complete, - input xon_gen_complete + (input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh, + input rx_clk, input rx_reset, input [15:0] rx_fifo_space, + input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req ); // ****************************************************************************** // Force our TX to send a PAUSE frame because our RX is nearly full // ****************************************************************************** - reg xon_int, xoff_int; + // RX Clock Domain + reg xon, xoff; reg [21:0] countdown; - - always @(posedge rx_clk or posedge rst) - if(rst) - begin - xon_int <= 0; - xoff_int <= 0; - end - else - begin - xon_int <= 0; - xoff_int <= 0; - if(pause_frame_send_en) - if(countdown == 0) - if(rx_fifo_space < fc_lwmark) - xoff_int <= 1; - else - ; - else - if(rx_fifo_space > fc_hwmark) - xon_int <= 1; - end // else: !if(rst) - - reg xoff_int_d1, xon_int_d1; - always @(posedge rx_clk) - xon_int_d1 <= xon_int; - always @(posedge rx_clk) - xoff_int_d1 <= xoff_int; + wire [15:0] pause_low_thresh = pause_thresh; + wire [15:0] pause_hi_thresh = 16'hFFFF; + wire [21:0] pq_reduced = {pause_time,6'd0} - 1700; - always @ (posedge tx_clk or posedge rst) - if (rst) - xoff_gen <=0; - else if (xoff_gen_complete) - xoff_gen <=0; - else if (xoff_int | xoff_int_d1) - xoff_gen <=1; + always @(posedge rx_clk) + if(rx_reset) + xoff <= 0; + else + xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh)); - always @ (posedge tx_clk or posedge rst) - if (rst) - xon_gen <=0; - else if (xon_gen_complete) - xon_gen <=0; - else if (xon_int | xon_int_d1) - xon_gen <=1; - - wire [15:0] pq_reduced = pause_quanta_set - 2; + always @(posedge rx_clk) + if(rx_reset) + xon <= 0; + else + xon <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh)); - always @(posedge tx_clk or posedge rst) - if(rst) + always @(posedge rx_clk) + if(rx_reset) countdown <= 0; - else if(xoff_gen) - countdown <= {pq_reduced,6'd0}; - else if(xon_gen) + else if(xoff) + countdown <= pq_reduced; + else if(xon) countdown <= 0; else if(countdown != 0) countdown <= countdown - 1; + + // Cross clock domains + oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx)); + oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx)); + + always @(posedge tx_clk) + if(xoff_tx) + pause_time_req <= pause_time; + else if(xon_tx) + pause_time_req <= 0; + + always @(posedge tx_clk) + if(tx_reset) + pause_req <= 0; + else + pause_req <= xon_tx | xoff_tx; -endmodule // flow_ctrl +endmodule // flow_ctrl_rx diff --git a/simple_gemac/simple_gemac.v b/simple_gemac/simple_gemac.v index 5ec2fa2ba..868a66819 100644 --- a/simple_gemac/simple_gemac.v +++ b/simple_gemac/simple_gemac.v @@ -6,7 +6,7 @@ module simple_gemac input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, // Flow Control Interface - input pause_req, input [15:0] pause_time, input pause_en, + input pause_req, input [15:0] pause_time_req, input pause_respect_en, // Settings input [47:0] ucast_addr, input [47:0] mcast_addr, @@ -33,7 +33,7 @@ module simple_gemac .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), .ifg(SGE_IFG), .mac_addr(ucast_addr), - .pause_req(pause_req), .pause_time(pause_time), // We request flow control + .pause_req(pause_req), .pause_time(pause_time_req), // We request flow control .pause_apply(pause_apply), .paused(paused) // We respect flow control ); @@ -50,7 +50,7 @@ module simple_gemac flow_ctrl_tx flow_ctrl_tx (.rst(rst_txclk), .tx_clk(tx_clk), - .tx_pause_en(pause_en), + .tx_pause_en(pause_respect_en), .pause_quanta(pause_quanta_rcvd), // 16 bit value .pause_quanta_val(pause_rcvd), .pause_apply(pause_apply), diff --git a/simple_gemac/simple_gemac_wb.v b/simple_gemac/simple_gemac_wb.v index cc2cdf7ec..6df277e3e 100644 --- a/simple_gemac/simple_gemac_wb.v +++ b/simple_gemac/simple_gemac_wb.v @@ -24,7 +24,9 @@ module simple_gemac_wb inout mdio, output mdc, output [47:0] ucast_addr, output [47:0] mcast_addr, output pass_ucast, output pass_mcast, output pass_bcast, - output pass_pause, output pass_all, output pause_en ); + output pass_pause, output pass_all, + output pause_respect_en, output pause_request_en, + output [15:0] pause_time, output [15:0] pause_thresh ); wire acc = wb_cyc & wb_stb; wire wr_acc = wb_cyc & wb_stb & wb_we; @@ -36,10 +38,10 @@ module simple_gemac_wb else wb_ack <= acc & ~wb_ack; - wire [5:0] misc_settings; - assign {pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en} = misc_settings; + wire [6:0] misc_settings; + assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings; - wb_reg #(.ADDR(0),.DEFAULT(6'b111001)) + wb_reg #(.ADDR(0),.DEFAULT(7'b0111001)) wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), .dat_i(wb_dat_i), .dat_o(misc_settings) ); wb_reg #(.ADDR(1),.DEFAULT(0)) @@ -131,6 +133,14 @@ module simple_gemac_wb .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); + wb_reg #(.ADDR(11),.DEFAULT(0)) + wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(pause_time) ); + + wb_reg #(.ADDR(12),.DEFAULT(0)) + wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(pause_thresh) ); + always @(posedge wb_clk) case(wb_adr[7:2]) 0 : wb_dat_o <= misc_settings; @@ -144,6 +154,8 @@ module simple_gemac_wb 8 : wb_dat_o <= MIICOMMAND; 9 : wb_dat_o <= MIISTATUS; 10: wb_dat_o <= MIIRX_DATA; + 11: wb_dat_o <= pause_time; + 12: wb_dat_o <= pause_thresh; endcase // case (wb_adr[7:2]) endmodule // simple_gemac_wb diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index de445476c..7511f3fb9 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -140,7 +140,12 @@ module simple_gemac_wrapper .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - wire [31:0] debug_tx, debug_rx; + flow_ctrl_rx flow_ctrl_rx + (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh), + .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space), + .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req)); + + wire [31:0] debug_tx, debug_rx; assign debug_tx = { { tx_ll_data }, { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile index 7847b8c72..94681f6cd 100644 --- a/top/u2_rev3/Makefile +++ b/top/u2_rev3/Makefile @@ -90,6 +90,7 @@ simple_gemac/simple_gemac_rx.v \ simple_gemac/crc.v \ simple_gemac/delay_line.v \ simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ simple_gemac/address_filter.v \ simple_gemac/ll8_to_txmac.v \ simple_gemac/rxmac_to_ll8.v \ -- cgit v1.2.3 From 38e0c588af094e7f809ad73981a3ba002d2c936d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Sep 2009 11:40:18 -0700 Subject: might as well use a cascade fifo to help timing and give a little more capacity --- simple_gemac/simple_gemac_wrapper.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index 7511f3fb9..71ad0cf0f 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -110,7 +110,7 @@ module simple_gemac_wrapper wire [35:0] tx_f36_data_int1; wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; - fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo + fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), -- cgit v1.2.3 From 42fc55415af499980901c7787f44c7e74b4a9ce1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Oct 2009 01:02:25 -0700 Subject: Fix warnings, mostly from implicitly defined wires or unspecified widths --- serdes/serdes_tx.v | 2 +- simple_gemac/flow_ctrl_rx.v | 1 + simple_gemac/simple_gemac.v | 3 ++- simple_gemac/simple_gemac_rx.v | 2 +- simple_gemac/simple_gemac_wrapper.v | 10 ++++++---- top/u2_core/u2_core.v | 4 +++- 6 files changed, 14 insertions(+), 8 deletions(-) (limited to 'simple_gemac/simple_gemac_wrapper.v') diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v index c74414e92..2e5e3bd80 100644 --- a/serdes/serdes_tx.v +++ b/serdes/serdes_tx.v @@ -84,7 +84,7 @@ module serdes_tx wire rd_eop_i = rd_flags_i[1]; wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused - wire have_data, empty; + wire have_data, empty, read; fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo (.clk(clk),.reset(rst),.clear(0), .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), diff --git a/simple_gemac/flow_ctrl_rx.v b/simple_gemac/flow_ctrl_rx.v index b13334d0e..d09bf377f 100644 --- a/simple_gemac/flow_ctrl_rx.v +++ b/simple_gemac/flow_ctrl_rx.v @@ -42,6 +42,7 @@ module flow_ctrl_rx countdown <= countdown - 1; // Cross clock domains + wire xon_tx, xoff_tx; oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx)); oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx)); diff --git a/simple_gemac/simple_gemac.v b/simple_gemac/simple_gemac.v index 868a66819..e7f327358 100644 --- a/simple_gemac/simple_gemac.v +++ b/simple_gemac/simple_gemac.v @@ -26,7 +26,8 @@ module simple_gemac reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk)); wire [15:0] pause_quanta_rcvd; - + wire pause_rcvd, pause_apply, paused; + simple_gemac_tx simple_gemac_tx (.clk125(clk125),.reset(rst_txclk), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), diff --git a/simple_gemac/simple_gemac_rx.v b/simple_gemac/simple_gemac_rx.v index bad43a607..45ddd6dfa 100644 --- a/simple_gemac/simple_gemac_rx.v +++ b/simple_gemac/simple_gemac_rx.v @@ -47,7 +47,7 @@ module simple_gemac_rx localparam DELAY = 6; delay_line #(.WIDTH(10)) rx_delay - (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_dl,rxd_del})); + (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del})); always @(posedge rx_clk) if(reset) diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index 71ad0cf0f..efcf89276 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -19,13 +19,15 @@ module simple_gemac_wrapper // MIIM inout mdio, output mdc, output [31:0] debug); - + + wire clear = 0; wire [7:0] rx_data, tx_data; wire tx_clk, tx_valid, tx_error, tx_ack; wire rx_clk, rx_valid, rx_error, rx_ack; wire [47:0] ucast_addr, mcast_addr; wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all; + wire pause_req; wire pause_request_en, pause_respect_en; wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; @@ -75,15 +77,15 @@ module simple_gemac_wrapper rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), - .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error), + .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); ll8_shortfifo rx_sfifo (.clk(rx_clk), .reset(rx_reset), .clear(0), .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), + .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); + .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2; diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 1f78f6d3d..03016e9b3 100755 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -525,9 +525,11 @@ module u2_core (.clk(wb_clk),.rst(wb_rst), .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we), - .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i), + .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]), .wb_ack_o(sd_ack) ); + assign sd_dat_i[31:8] = 0; + // ///////////////////////////////////////////////////////////////////////// // DSP wire [31:0] sample_rx, sample_tx; -- cgit v1.2.3