From 42fc55415af499980901c7787f44c7e74b4a9ce1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Oct 2009 01:02:25 -0700 Subject: Fix warnings, mostly from implicitly defined wires or unspecified widths --- serdes/serdes_tx.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'serdes/serdes_tx.v') diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v index c74414e92..2e5e3bd80 100644 --- a/serdes/serdes_tx.v +++ b/serdes/serdes_tx.v @@ -84,7 +84,7 @@ module serdes_tx wire rd_eop_i = rd_flags_i[1]; wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused - wire have_data, empty; + wire have_data, empty, read; fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo (.clk(clk),.reset(rst),.clear(0), .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), -- cgit v1.2.3