From 5a17f48e7374466b10787ef2721166b1bb862cf1 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Mon, 16 Apr 2007 21:30:13 +0000 Subject: Adds capability to independently delay the Auto T/R switching signal by a configurable number of clock ticks, to allow users to precisely align their T/R output with the pipeline delays in the transmitter. There are two new registers: FR_ATR_TX_DELAY (7'd2) FR_ATR_RX_DELAY (7'd3) ...and the corresponding db_base.py methods to set them: db_base.set_atr_tx_delay(clock_ticks) db_base.set_atr_rx_delay(clock_ticks) These methods are inherited by all the daughterboard objects so you can call them from your scripts as: subdev.set_atr_tx_delay(...) ...where 'subdev' represents the daughtercard object you're working with. The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%, with no additional synthesis messages or impact on timing. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5 --- rbf/rev4/std_2rxhb_2tx.rbf | Bin 179750 -> 180404 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'rbf/rev4') diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf index dbcd84e2d..2b97f9d4e 100755 Binary files a/rbf/rev4/std_2rxhb_2tx.rbf and b/rbf/rev4/std_2rxhb_2tx.rbf differ -- cgit v1.2.3