From 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e Mon Sep 17 00:00:00 2001 From: jcorgan Date: Mon, 8 Sep 2008 01:00:12 +0000 Subject: Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5 --- opencores/i2c/bench/verilog/CVS/Entries | 5 +++++ opencores/i2c/bench/verilog/CVS/Repository | 1 + opencores/i2c/bench/verilog/CVS/Root | 1 + opencores/i2c/bench/verilog/CVS/Template | 0 4 files changed, 7 insertions(+) create mode 100644 opencores/i2c/bench/verilog/CVS/Entries create mode 100644 opencores/i2c/bench/verilog/CVS/Repository create mode 100644 opencores/i2c/bench/verilog/CVS/Root create mode 100644 opencores/i2c/bench/verilog/CVS/Template (limited to 'opencores/i2c/bench/verilog/CVS') diff --git a/opencores/i2c/bench/verilog/CVS/Entries b/opencores/i2c/bench/verilog/CVS/Entries new file mode 100644 index 000000000..2dd779100 --- /dev/null +++ b/opencores/i2c/bench/verilog/CVS/Entries @@ -0,0 +1,5 @@ +/i2c_slave_model.v/1.7/Mon Sep 4 09:08:51 2006// +/spi_slave_model.v/1.1/Sat Feb 28 15:32:54 2004// +/tst_bench_top.v/1.8/Mon Sep 4 09:08:51 2006// +/wb_master_model.v/1.4/Sat Feb 28 15:40:42 2004// +D diff --git a/opencores/i2c/bench/verilog/CVS/Repository b/opencores/i2c/bench/verilog/CVS/Repository new file mode 100644 index 000000000..b37c379e9 --- /dev/null +++ b/opencores/i2c/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/bench/verilog diff --git a/opencores/i2c/bench/verilog/CVS/Root b/opencores/i2c/bench/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/i2c/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/i2c/bench/verilog/CVS/Template b/opencores/i2c/bench/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb -- cgit v1.2.3