From aeaea4936011665e2bbad66e1fdf4628e2b940f2 Mon Sep 17 00:00:00 2001 From: Trung N Tran Date: Tue, 29 Aug 2017 12:11:05 -0700 Subject: mpm: add n310 motherboard revD support This will enable both RevC and RevD from an MPM perspective. The revision read back from the EEPROM is used to enable the code for either rev. The impact on the code is limited to the port expander GPIOs. Port expander objects are instantiated in both the N310 MPM module as well as the n3xx_bist executable. --- mpm/python/n3xx_bist | 16 +++- mpm/python/usrp_mpm/periph_manager/n310.py | 115 +++++++++++++++++++---------- 2 files changed, 91 insertions(+), 40 deletions(-) (limited to 'mpm') diff --git a/mpm/python/n3xx_bist b/mpm/python/n3xx_bist index 0f3d89de2..55ce0f57f 100755 --- a/mpm/python/n3xx_bist +++ b/mpm/python/n3xx_bist @@ -226,6 +226,7 @@ def expand_options(option_list): 'spam': 'eggs'}. """ return dict(x.split('=') for x in option_list) + ############################################################################## # Bist class ############################################################################## @@ -238,6 +239,7 @@ class N310BIST(object): 'standard': ["ddr3", "gpsdo", "rtc", "temp", "clock_int", "tpm"], 'extended': "*", } + REV = 3 @staticmethod def make_arg_parser(): @@ -281,6 +283,14 @@ class N310BIST(object): def __init__(self): self.args = N310BIST.make_arg_parser().parse_args() self.args.option = expand_options(self.args.option) + try: + from usrp_mpm.periph_manager.n310 import n310 + default_rev = n310.mboard_max_rev + except ImportError: + # This means we're in dry run mode or something like that, so just + # pick something + default_rev = 3 + self.mb_rev = int(self.args.option.get('mb_rev', default_rev)) self.tests_to_run = set() for test in self.args.tests: if test in self.collections: @@ -296,7 +306,7 @@ class N310BIST(object): get_main_logger().setLevel(WARNING) self.log = get_main_logger().getChild('main') except ImportError: - pass + print("No logging capability available.") def expand_collection(self, coll): """ @@ -448,8 +458,8 @@ class N310BIST(object): "mode": 3 } from usrp_mpm.periph_manager import n310 + gpio_tca6424 = n310.TCA6424(self.mb_rev) # Turn on GPS, give some time to acclimatize - gpio_tca6424 = n310.TCA6424() gpio_tca6424.set("PWREN-GPS") time.sleep(5) gps_warmup_timeout = float( @@ -678,7 +688,7 @@ class N310BIST(object): 'read_patterns': list(patterns), } from usrp_mpm.periph_manager import n310 - gpio_tca6424 = n310.TCA6424() + gpio_tca6424 = n310.TCA6424(self.REV) gpio_tca6424.set("FPGA-GPIO-EN") # Allow some time for the front-panel GPIOs to become usable time.sleep(.5) diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index f855f2f3f..c6ae10241 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -32,7 +32,6 @@ from ..sysfs_gpio import SysFSGPIO from ..ethtable import EthDispatcherTable from .. import libpyusrp_periphs as lib - N3XX_DEFAULT_EXT_CLOCK_FREQ = 10e6 N3XX_DEFAULT_CLOCK_SOURCE = 'external' N3XX_DEFAULT_TIME_SOURCE = 'internal' @@ -42,38 +41,74 @@ N3XX_DEFAULT_ENABLE_FPGPIO = True class TCA6424(object): """ Abstraction layer for the port/gpio expander + pins_list is an array of different version of TCA6424 pins map. + First element of this array corresponding to revC, second is revD etc... """ - pins = ( - 'PWREN-CLK-MGT156MHz', - 'PWREN-CLK-WB-CDCM', - 'WB-CDCM-RESETn', - 'WB-CDCM-PR0', - 'WB-CDCM-PR1', - 'WB-CDCM-OD0', - 'WB-CDCM-OD1', - 'WB-CDCM-OD2', - 'PWREN-CLK-MAINREF', - 'CLK-MAINREF-SEL1', - 'CLK-MAINREF-SEL0', - '12', - '13', - 'FPGA-GPIO-EN', - 'PWREN-CLK-WB-20MHz', - 'PWREN-CLK-WB-25MHz', - 'GPS-PHASELOCK', - 'GPS-nINITSURV', - 'GPS-nRESET', - 'GPS-WARMUP', - 'GPS-SURVEY', - 'GPS-LOCKOK', - 'GPS-ALARM', - 'PWREN-GPS', - ) - - def __init__(self): + pins_list = [ + ( + 'PWREN-CLK-MGT156MHz', + 'NETCLK-CE', #revC name: 'PWREN-CLK-WB-CDCM', + 'NETCLK-RESETn', #revC name: 'WB-CDCM-RESETn', + 'NETCLK-PR0', #revC name: 'WB-CDCM-PR0', + 'NETCLK-PR1', #revC name: 'WB-CDCM-PR1', + 'NETCLK-OD0', #revC name: 'WB-CDCM-OD0', + 'NETCLK-OD1', #revC name: 'WB-CDCM-OD1', + 'NETCLK-OD2', #revC name: 'WB-CDCM-OD2', + 'PWREN-CLK-MAINREF', + 'CLK-MAINSEL-25MHz', #revC name: 'CLK-MAINREF-SEL1', + 'CLK-MAINSEL-EX_B', #revC name: 'CLK-MAINREF-SEL0', + '12', + 'CLK-MAINSEL-GPS', #revC name: '13', + 'FPGA-GPIO-EN', + 'PWREN-CLK-WB-20MHz', + 'PWREN-CLK-WB-25MHz', + 'GPS-PHASELOCK', + 'GPS-nINITSURV', + 'GPS-nRESET', + 'GPS-WARMUP', + 'GPS-SURVEY', + 'GPS-LOCKOK', + 'GPS-ALARM', + 'PWREN-GPS', + ), + ( + 'NETCLK-PR1', + 'NETCLK-PR0', + 'NETCLK-CE', + 'NETCLK-RESETn', + 'NETCLK-OD2', + 'NETCLK-OD1', + 'NETCLK-OD0', + 'PWREN-CLK-MGT156MHz', + 'PWREN-CLK-MAINREF', + 'CLK-MAINSEL-25MHz', + 'CLK-MAINSEL-EX_B', + '12', + 'CLK-MAINSEL-GPS', + 'FPGA-GPIO-EN', + 'PWREN-CLK-WB-20MHz', + 'PWREN-CLK-WB-25MHz', + 'GPS-PHASELOCK', + 'GPS-nINITSURV', + 'GPS-nRESET', + 'GPS-WARMUP', + 'GPS-SURVEY', + 'GPS-LOCKOK', + 'GPS-ALARM', + 'PWREN-GPS', + )] + + def __init__(self, rev): # Default state: Turn on GPS power, take GPS out of reset or # init-survey, turn on 156.25 MHz clock - self._gpios = SysFSGPIO('tca6424', 0xFFE7FF, 0x86E7FF, 0x860001) + # min Support from revC or rev = 2 + if rev == 2: + self.pins = self.pins_list[0] + else: + self.pins = self.pins_list[1] + + default_val = 0x860101 if rev == 2 else 0x860780 + self._gpios = SysFSGPIO('tca6424', 0xFFF7FF, 0x86F7FF, default_val) def set(self, name, value=None): """ @@ -95,6 +130,7 @@ class TCA6424(object): assert name in self.pins return self._gpios.get(self.pins.index(name)) + class FP_GPIO(object): """ Abstraction layer for the front panel GPIO @@ -191,7 +227,8 @@ class n310(PeriphManagerBase): super(n310, self).__init__(args) # Init peripherals self.log.trace("Initializing TCA6424 port expander controls...") - self._gpios = TCA6424() + self._gpios = TCA6424(int(self.mboard_info['rev'])) + self.log.trace("Enabling power of MGT156MHZ clk") self._gpios.set("PWREN-CLK-MGT156MHz") self.enable_gps( enable=bool( @@ -353,14 +390,18 @@ class n310(PeriphManagerBase): assert clock_source in self.get_clock_sources() self.log.trace("Setting clock source to `{}'".format(clock_source)) if clock_source == 'internal': - self._gpios.set("CLK-MAINREF-SEL0") - self._gpios.set("CLK-MAINREF-SEL1") + self._gpios.set("CLK-MAINSEL-EX_B") + self._gpios.set("CLK-MAINSEL-25MHz") + self._gpios.reset("CLK-MAINSEL-GPS") elif clock_source == 'gpsdo': - self._gpios.set("CLK-MAINREF-SEL0") - self._gpios.reset("CLK-MAINREF-SEL1") + self._gpios.set("CLK-MAINSEL-EX_B") + self._gpios.reset("CLK-MAINSEL-25MHz") + self._gpios.set("CLK-MAINSEL-GPS") else: # external - self._gpios.reset("CLK-MAINREF-SEL0") - self._gpios.reset("CLK-MAINREF-SEL1") + self._gpios.reset("CLK-MAINSEL-EX_B") + self._gpios.reset("CLK-MAINSEL-GPS") + # SKY13350 needs to be in known state + self._gpios.set("CLK-MAINSEL-25MHz") self._clock_source = clock_source ref_clk_freq = self.get_ref_clock_freq() self.log.info("Reference clock frequency is: {} MHz".format( -- cgit v1.2.3