From 0280a82aa00f340bf7de11f97fafc11424ba4f1e Mon Sep 17 00:00:00 2001 From: Mark Meserve Date: Wed, 14 Aug 2019 17:38:56 -0500 Subject: e320: fix time source clobbering ref source - Fixes a case where the e320 would be unable to lock to an external 10 MHz reference - Previously, calling set_time_source would set the reference clock source to internal as a side effect --- mpm/python/usrp_mpm/periph_manager/e320_periphs.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'mpm') diff --git a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py index fa8ad30b2..0cf7f59c6 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py @@ -259,11 +259,15 @@ class MboardRegsControl(object): pps_sel_val = 0b1 << self.MB_CLOCK_CTRL_PPS_SEL_EXT else: assert False, "Cannot set to invalid time source: {}".format(time_source) + + pps_sel_mask = ((0b1 << self.MB_CLOCK_CTRL_PPS_SEL_INT) | + (0b1 << self.MB_CLOCK_CTRL_PPS_SEL_EXT)) with self.regs: - reg_val = self.peek32(self.MB_CLOCK_CTRL) & 0xFFFFFF90 # prevent glitches by writing a cleared value first, then the final value. + reg_val = self.peek32(self.MB_CLOCK_CTRL) & ~pps_sel_mask + self.log.trace("Writing MB_CLOCK_CTRL to 0x{:08X}".format(reg_val)) self.poke32(self.MB_CLOCK_CTRL, reg_val) - reg_val = reg_val | (pps_sel_val & 0x6F) + reg_val = reg_val | pps_sel_val self.log.trace("Writing MB_CLOCK_CTRL to 0x{:08X}".format(reg_val)) self.poke32(self.MB_CLOCK_CTRL, reg_val) -- cgit v1.2.3