From 267365c9458690842da549a00b7adb7946a1117d Mon Sep 17 00:00:00 2001 From: Samuel O'Brien Date: Wed, 5 Aug 2020 09:29:41 -0500 Subject: sim: Clarify Naming of Streams ChdrSniffer is renamed to ChdrEndpoint to clarify its function as the actual destination of chdr packets, rather than just an observer. TxWorker has been renamed to OutputStream and RxWorker has been renamed to InputStream to avoid ambiguities regarding Tx and Rx terminology. Signed-off-by: Samuel O'Brien --- mpm/python/usrp_mpm/periph_manager/sim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'mpm/python/usrp_mpm/periph_manager') diff --git a/mpm/python/usrp_mpm/periph_manager/sim.py b/mpm/python/usrp_mpm/periph_manager/sim.py index 7f9a610a7..20d2486c0 100644 --- a/mpm/python/usrp_mpm/periph_manager/sim.py +++ b/mpm/python/usrp_mpm/periph_manager/sim.py @@ -16,7 +16,7 @@ from usrp_mpm.mpmlog import get_logger from usrp_mpm.rpc_server import no_claim from usrp_mpm.periph_manager import PeriphManagerBase from usrp_mpm.simulator.sim_dboard_catalina import SimulatedCatalinaDboard -from usrp_mpm.simulator.chdr_sniffer import ChdrSniffer +from usrp_mpm.simulator.chdr_endpoint import ChdrEndpoint CLOCK_SOURCE_INTERNAL = "internal" @@ -83,7 +83,7 @@ class sim(PeriphManagerBase): super().__init__() self.device_id = 1 - self.chdr_sniffer = ChdrSniffer(self.log, args) + self.chdr_endpoint = ChdrEndpoint(self.log, args) # Unlike the real hardware drivers, if there is an exception here, # we just crash. No use missing an error when testing. -- cgit v1.2.3