From ba00ff0cf5c0ced093e0be12b3006fe2f657a58a Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Mon, 21 Feb 2022 11:17:25 +0100 Subject: Remove FSRU-related files The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA repository never had the relevant files, and the block controller also never existed. This removes all the corresponding files from MPM, as well as some references from makefiles. --- mpm/python/usrp_mpm/periph_manager/n3xx.py | 3 --- 1 file changed, 3 deletions(-) (limited to 'mpm/python/usrp_mpm/periph_manager/n3xx.py') diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py index 09386106d..2fbb12365 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py @@ -28,7 +28,6 @@ from usrp_mpm.periph_manager.n3xx_periphs import BackpanelGPIO from usrp_mpm.periph_manager.n3xx_periphs import MboardRegsControl from usrp_mpm.periph_manager.n3xx_periphs import RetimerQSFP from usrp_mpm.dboard_manager.magnesium import Magnesium -from usrp_mpm.dboard_manager.eiscat import EISCAT from usrp_mpm.dboard_manager.rhodium import Rhodium N3XX_DEFAULT_EXT_CLOCK_FREQ = 10e6 @@ -49,7 +48,6 @@ N3XX_FPGPIO_WIDTH = 12 # Import daughterboard PIDs from their respective classes MG_PID = Magnesium.pids[0] -EISCAT_PID = EISCAT.pids[0] RHODIUM_PID = Rhodium.pids[0] ############################################################################### @@ -109,7 +107,6 @@ class n3xx(ZynqComponents, PeriphManagerBase): # still use the n310.bin image. # We'll leave this here for # debugging purposes. - ('n310', (EISCAT_PID , EISCAT_PID )): 'eiscat', ('n310', (RHODIUM_PID, RHODIUM_PID)): 'n320', ('n310', (RHODIUM_PID, )): 'n320', } -- cgit v1.2.3