From 4a4d1d797f486e6e0ecb18c4890d2f4715c03000 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Fri, 13 Jul 2018 17:05:38 -0700 Subject: mpm: mg: Move RF cal initialization after JESD init --- mpm/python/usrp_mpm/dboard_manager/mg_init.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'mpm/python/usrp_mpm/dboard_manager') diff --git a/mpm/python/usrp_mpm/dboard_manager/mg_init.py b/mpm/python/usrp_mpm/dboard_manager/mg_init.py index 34016e9f5..fccdc2e27 100644 --- a/mpm/python/usrp_mpm/dboard_manager/mg_init.py +++ b/mpm/python/usrp_mpm/dboard_manager/mg_init.py @@ -452,8 +452,6 @@ class MagnesiumInitManager(object): time.sleep(0.001) # 17us... ish. jesdcore.send_sysref_pulse() async_exec(self.mykonos, "finish_initialization") - # TODO:can we call this after JESD? - self.init_rf_cal(args) self.log.trace("Starting JESD204b Link Initialization...") # Generally, enable the source before the sink. Start with the DAC side. self.log.trace("Starting FPGA framer...") @@ -545,6 +543,7 @@ class MagnesiumInitManager(object): self.init_jesd(jesdcore, master_clock_rate, args) jesdcore = None # Help with garbage collection # That's all that requires access to the dboard regs! + self.init_rf_cal(args) if bool(args.get('rfic_digital_loopback')): self.log.warning( "RF Functionality Disabled: JESD204b digital loopback " -- cgit v1.2.3