From 14fb3cc6f4c63303a7f35b81087c31eb494f7166 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Fri, 8 Nov 2019 15:56:46 -0800 Subject: e310: Fix issues in MPM and UHD - Remove superfluous INFO logging - Improve formatting in many places - Improve Pylint score in various places - Add tear_down to DB object - Simplify custom EEPROM code for E310 - Fix time source selection code - Remove references to GPS_CTRL and GPS_STATUS (are E320 only) - Move clock source control out of MboardRegs object --- mpm/python/usrp_mpm/dboard_manager/e31x_db.py | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'mpm/python/usrp_mpm/dboard_manager') diff --git a/mpm/python/usrp_mpm/dboard_manager/e31x_db.py b/mpm/python/usrp_mpm/dboard_manager/e31x_db.py index add77553f..8c38fa652 100644 --- a/mpm/python/usrp_mpm/dboard_manager/e31x_db.py +++ b/mpm/python/usrp_mpm/dboard_manager/e31x_db.py @@ -126,6 +126,18 @@ class E31x_db(DboardManagerBase): self.set_catalina_clock_rate(self.master_clock_rate) return True + def tear_down(self): + """ + De-init this object as much as possible. + """ + self.log.trace("Tearing down E310 DB object!") + for method in [ + x for x in dir(self.catalina) + if not x.startswith("_") and \ + callable(getattr(self.catalina, x))]: + delattr(self, method) + self.catalina = None + def get_master_clock_rate(self): " Return master clock rate (== sampling rate) " return self.master_clock_rate @@ -197,7 +209,7 @@ class E31x_db(DboardManagerBase): """ Async call to catalina set_clock_rate """ - self.log.trace("Setting Clock rate to {}".format(rate)) + self.log.trace("Setting Clock rate to {} MHz".format(rate/1e6)) async_exec(lib.ad9361, "set_clock_rate", self.catalina, rate) return rate -- cgit v1.2.3