From 5a5f604994902770382f0aa8447a511077160a28 Mon Sep 17 00:00:00 2001 From: Ryan Marlow Date: Wed, 25 Jul 2018 18:22:59 -0700 Subject: uhd/mpm: eiscat: Various changes - correct lmk initialization parameters - adding missing parameters and consts wrt clock synchronization. - fixed default master clock rate - eiscat, ddc: update xml. - remove references to CORDIC_FREQ in ddc_eiscat - update readback reg addr in radio_eiscat - set default spp from 3992 to 3968. - updated jesd mode sequence initialization - updating eiscat_radio_ctrl_impl - add rx_codecs to property tree to display correct ADC chip. - updated issue_stream_cmd --- mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py') diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py index c2f35232d..509d65be0 100644 --- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py @@ -14,8 +14,8 @@ class LMK04828EISCAT(LMK04828): """ LMK04828 controls for EISCAT daughterboard """ - def __init__(self, regs_iface, ref_clock_freq, slot=None): - LMK04828.__init__(self, regs_iface, slot) + def __init__(self, regs_iface, ref_clock_freq, slot=None, log=None): + LMK04828.__init__(self, regs_iface, log) self.log.trace("Using reference clock frequency {} MHz".format(ref_clock_freq/1e6)) if ref_clock_freq != 10e6: error_msg = "Invalid reference clock frequency: {} MHz. " \ @@ -26,6 +26,13 @@ class LMK04828EISCAT(LMK04828): self.init() self.config() + + def get_vco_freq(self): + """ + Return the hard coded VCO frequency in the LMK PLL2. + """ + return 2.496e9 + def init(self): """ Basic init. Turns it on. Let's us read SPI. -- cgit v1.2.3