From a44f791a44fc248f82da070cd6ea2405cf4532f6 Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Tue, 7 Jul 2015 15:13:11 -0700 Subject: x300: Added FPGA->ADC Clock delay for rev 7+ boards --- host/lib/usrp/x300/x300_clock_ctrl.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host') diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index d9c3a1177..350e9e9bc 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -52,7 +52,7 @@ static const x300_clk_delays X300_REV0_6_CLK_DELAYS = x300_clk_delays( /*fpga=*/0.900, /*adc=*/0.000, /*dac=*/0.900, /*db_rx=*/0.000, /*db_tx=*/0.000); static const x300_clk_delays X300_REV7_CLK_DELAYS = x300_clk_delays( - /*fpga=*/0.900, /*adc=*/0.000, /*dac=*/0.900, /*db_rx=*/0.000, /*db_tx=*/0.000); + /*fpga=*/0.000, /*adc=*/4.400, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); using namespace uhd; -- cgit v1.2.3