From 9335939b9b3ab85cee5908ff3357f9e7819e3366 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Mon, 12 Jul 2021 13:54:33 -0500 Subject: fpga: x400: Add GPIO control via ATR and DB state --- host/docs/res/x4xx_dio_source_muxes.svg | 3 +++ host/docs/usrp_x4xx.dox | 33 +++++++++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) create mode 100644 host/docs/res/x4xx_dio_source_muxes.svg (limited to 'host') diff --git a/host/docs/res/x4xx_dio_source_muxes.svg b/host/docs/res/x4xx_dio_source_muxes.svg new file mode 100644 index 000000000..cce38f226 --- /dev/null +++ b/host/docs/res/x4xx_dio_source_muxes.svg @@ -0,0 +1,3 @@ + + +01S0
Mux
Mux
User Application
User Application
Radio#0 DIO ATR
Radio#0 DIO ATR
DIO_MASTER
DIO_MAS...
Digital Interface Block Radio#0
Digital Interface Bl...
To DIO Aux
 Board
To DIO...
Controlled By Radio#0
Control...01S0
Mux
Mux
SW_DIO_CONTROL
SW_DIO_...
PS
PS
MPM
MPM01S0
Mux
Mux
DIO_SOURCE
DIO_SOU...01S0
Mux
Mux
DIO_OVERRIDE
DIO_OVE...01S0
Mux
Mux
RADIO_SOURCE
RADIO_S...01S0
Mux
Mux
IINTERFACE_DIO_SELECT
IINTERF...
Radio#1 DIO ATR
Radio#1 DIO ATR
Digital Interface Block Radio#1
Digital Interface Bl...
Controlled By Radio#1
Control...Viewer does not support full SVG 1.1 \ No newline at end of file diff --git a/host/docs/usrp_x4xx.dox b/host/docs/usrp_x4xx.dox index 3c744de36..2ed5863ab 100644 --- a/host/docs/usrp_x4xx.dox +++ b/host/docs/usrp_x4xx.dox @@ -832,10 +832,35 @@ GPS lock is reported. \subsection x4xx_usage_gpio Front-Panel Programmable GPIOs The USRP X410 has two HDMI front-panel connectors, which are connected to the -FPGA. - -Support for using these with UHD is not yet available. - +FPGA. For a description of the GPIO control API, see \ref x4x0gpio_fpanel. + +There are multiple sources that can control the state of the GPIO lines. +UHD has the capability of controlling which source each pin is driven from. +The source control block is located in the X4x0 core logic block in the FPGA, and is also accessible +via MPM. There are also local registers in the source control block that control the state +of GPIOs manually if none of the additionally supported control schemes are required. + +Source selection is performed via an array of muxes, each accessible via an independent register. +The diagram below indicates the arrangement of muxes controlling GPIO source selection. +\image html x4xx_dio_source_muxes.svg "X4x0 GPIO Source Control" width=60% + +UHD has access to all radio-controlled blocks. In the diagram above, this includes +one ATR DIO control block and one digital interface block for each radio. + +When ATR control is selected as the source, it uses the Daughterboard state to determine +the behavior of the GPIOs. The Daughterboard state is the concatenation of the +transmission state of all channels in the daughterboard. + +The Digital Interface Block currently supports a variable rate SPI bus. Having +one of these blocks for each radio grants the ability to have two SPI engines +running simultaneously. Each engine has the ability to service multiple slaves, +but transactions can only be issued to one slave at a time. Slaves are customizable, +and clock rate, instruction length, edge polarity are accommodated for based on the +currently selected slave. Mapping of SPI signals to DIO port pins is also customizable. +See \ref x4x0_spi_iface. + +Mapping from any source to the front-panel connectors is performed in a per-pin basis, +allowing the user to interact with each connector pin from any radio. \subsection x4xx_usage_subdevspec Subdev Specifications -- cgit v1.2.3