From 32ef40a27292f74ccaef9ae5088e22af7bba3e2b Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Fri, 22 Jun 2018 15:53:25 +0100
Subject: RFNoC: Add moving avg, splitstream, and vector IIR block definitions

---
 host/include/uhd/rfnoc/blocks/moving_avg.xml  | 50 ++++++++++++++++
 host/include/uhd/rfnoc/blocks/splitstream.xml | 38 ++++++++++++
 host/include/uhd/rfnoc/blocks/vector_iir.xml  | 84 +++++++++++++++++++++++++++
 3 files changed, 172 insertions(+)
 create mode 100644 host/include/uhd/rfnoc/blocks/moving_avg.xml
 create mode 100644 host/include/uhd/rfnoc/blocks/splitstream.xml
 create mode 100644 host/include/uhd/rfnoc/blocks/vector_iir.xml

(limited to 'host')

diff --git a/host/include/uhd/rfnoc/blocks/moving_avg.xml b/host/include/uhd/rfnoc/blocks/moving_avg.xml
new file mode 100644
index 000000000..943c83261
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/moving_avg.xml
@@ -0,0 +1,50 @@
+<!--This defines one NoC-Block.-->
+<nocblock>
+  <name>Moving Average</name>
+  <blockname>MovingAverage</blockname>
+  <ids>
+    <id revision="0">AAD2</id>
+  </ids>
+  <!-- Registers -->
+  <registers>
+    <setreg>
+      <name>SUM_LEN</name>
+      <address>192</address>
+    </setreg>
+    <setreg>
+      <name>DIVISOR</name>
+      <address>193</address>
+    </setreg>
+    <readback>
+      <name>RB_SUM_LEN</name>
+      <address>0</address>
+    </readback>
+    <readback>
+      <name>RB_DIVISOR</name>
+      <address>1</address>
+    </readback>
+  </registers>
+  <!-- Args -->
+  <args>
+    <arg>
+      <name>length</name>
+      <type>int</type>
+      <value>10</value>
+      <check>GE($length, 1) AND LE($length, 255)</check>
+      <check_message>Average length must be in [1, 255].</check_message>
+      <action>SR_WRITE("SUM_LEN", $length) AND SR_WRITE("DIVISOR", $length)</action>
+    </arg>
+  </args>
+  <!-- Ports -->
+  <ports>
+    <sink>
+      <name>in</name>
+      <type>sc16</type>
+      <port>0</port>
+    </sink>
+    <source>
+      <name>avg</name>
+      <type>sc16</type>
+    </source>
+  </ports>
+</nocblock>
diff --git a/host/include/uhd/rfnoc/blocks/splitstream.xml b/host/include/uhd/rfnoc/blocks/splitstream.xml
new file mode 100644
index 000000000..08cbd0457
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/splitstream.xml
@@ -0,0 +1,38 @@
+<!--This defines one NoC-Block.-->
+<nocblock>
+  <name>Split Stream</name>
+  <blockname>SplitStream</blockname>
+  <!--There can be several of these:-->
+  <ids>
+    <id revision="0">5757</id>
+  </ids>
+  <!-- This block takes any type, hence we skip the <type> tag: -->
+  <ports>
+    <sink>
+      <name>in</name>
+    </sink>
+    <source>
+      <name>out0</name>
+    </source>
+    <source>
+      <name>out1</name>
+    </source>
+  </ports>
+  <!--<components>-->
+    <!--<component>-->
+      <!--<key revision="1">nocshell</key>-->
+    <!--</component>-->
+    <!--<component srbase="0">-->
+      <!--[>Will look for a component with this key:<]-->
+      <!--<key revision="1">componentname</key>-->
+    <!--</component>-->
+  <!--</components>-->
+  <!--<connection>-->
+    <!--<source port="0">nocshell</source>-->
+    <!--<sink port="0">componentname</sink>-->
+  <!--</connection>-->
+  <!--<connection>-->
+    <!--<source port="0">componentname</source>-->
+    <!--<sink port="0">nocshell</sink>-->
+  <!--</connection>-->
+</nocblock>
diff --git a/host/include/uhd/rfnoc/blocks/vector_iir.xml b/host/include/uhd/rfnoc/blocks/vector_iir.xml
new file mode 100644
index 000000000..98b46e757
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/vector_iir.xml
@@ -0,0 +1,84 @@
+<!--This defines one NoC-Block.-->
+<nocblock>
+  <name>Vector IIR</name>
+  <blockname>VectorIIR</blockname>
+  <!--There can be several of these:-->
+  <ids>
+    <id revision="0">1112</id>
+  </ids>
+  <!-- Registers -->
+  <registers>
+    <setreg>
+      <name>VECTOR_LEN</name>
+      <address>129</address>
+    </setreg>
+    <setreg>
+      <name>ALPHA</name>
+      <address>130</address>
+    </setreg>
+    <setreg>
+      <name>BETA</name>
+      <address>131</address>
+    </setreg>
+  </registers>
+  <!-- Args -->
+  <args>
+    <arg>
+      <name>spp</name>
+      <type>int</type>
+      <value>256</value>
+      <check>GE($spp, 1) AND LE($spp, 4096)</check>
+      <check_message>Vector length must be in [1, 4096].</check_message>
+      <action>SR_WRITE("VECTOR_LEN", $spp)</action>
+    </arg>
+    <arg>
+      <name>alpha</name>
+      <type>double</type>
+      <value>0.9</value>
+      <check>GT($alpha, 0.0) AND LT($alpha, 1.0)</check>
+      <check_message>Alpha must be in (0.0, 1.0).</check_message>
+      <!--We set the register value to alpha * 2^31 (Q1.31 format)-->
+      <action>SR_WRITE("ALPHA", IROUND(MULT($alpha, 2147483648.0)))</action>
+    </arg>
+    <arg>
+      <name>beta</name>
+      <type>double</type>
+      <value>0.1</value>
+      <check>GT($beta, 0.0) AND LT($beta, 1.0)</check>
+      <check_message>Beta must be in (0.0, 1.0).</check_message>
+      <!--We set the register value to alpha * 2^31 (Q1.31 format)-->
+      <action>SR_WRITE("BETA", IROUND(MULT($beta, 2147483648.0)))</action>
+    </arg>
+  </args>
+  <ports>
+    <sink>
+      <name>in</name>
+      <type>sc16</type>
+      <vlen>$spp</vlen>
+      <pkt_size>%vlen</pkt_size>
+    </sink>
+    <source>
+      <name>out</name>
+      <type>sc16</type>
+      <vlen>$spp</vlen>
+      <pkt_size>%vlen</pkt_size>
+    </source>
+  </ports>
+  <!--<components>-->
+    <!--<component>-->
+      <!--<key revision="1">nocshell</key>-->
+    <!--</component>-->
+    <!--<component srbase="0">-->
+      <!--[>Will look for a component with this key:<]-->
+      <!--<key revision="1">componentname</key>-->
+    <!--</component>-->
+  <!--</components>-->
+  <!--<connection>-->
+    <!--<source port="0">nocshell</source>-->
+    <!--<sink port="0">componentname</sink>-->
+  <!--</connection>-->
+  <!--<connection>-->
+    <!--<source port="0">componentname</source>-->
+    <!--<sink port="0">nocshell</sink>-->
+  <!--</connection>-->
+</nocblock>
-- 
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