From 0e34dd98c90160f6ff2905007efbc1e7a76e6928 Mon Sep 17 00:00:00 2001 From: Jason Abele Date: Tue, 4 May 2010 12:01:27 -0700 Subject: Fixed SPI register length --- host/lib/ic_reg_maps/gen_adf4350_regs.py | 4 ++-- host/lib/usrp/dboard/db_wbx.cpp | 29 +++++++++++++++++++---------- 2 files changed, 21 insertions(+), 12 deletions(-) (limited to 'host') diff --git a/host/lib/ic_reg_maps/gen_adf4350_regs.py b/host/lib/ic_reg_maps/gen_adf4350_regs.py index 924139936..8cc6fd16c 100755 --- a/host/lib/ic_reg_maps/gen_adf4350_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4350_regs.py @@ -34,7 +34,7 @@ int_16_bit 0[15:30] 23 ## address 1 ######################################################################## mod_12_bit 1[3:14] fff -phase_12_bit 1[15:26] 1 +phase_12_bit 1[15:26] 0 prescaler 1[27] 0 4_5, 8_9 ##reserved 1[28:31] 0 ######################################################################## @@ -52,7 +52,7 @@ double_buffer 2[13] 0 disabled, enabled r_counter_10_bit 2[14:23] 0 reference_divide_by_2 2[24] 1 disabled, enabled reference_doubler 2[25] 0 disabled, enabled -muxout 2[26:28] 3 3state, dvdd, dgnd, rdiv, ndiv, analog_ld, dld, reserved +muxout 2[26:28] 1 3state, dvdd, dgnd, rdiv, ndiv, analog_ld, dld, reserved low_noise_and_spur 2[29:30] 3 low_noise, reserved0, reserved1, low_spur ######################################################################## ## address 3 diff --git a/host/lib/usrp/dboard/db_wbx.cpp b/host/lib/usrp/dboard/db_wbx.cpp index c34c92a55..16bbf7719 100644 --- a/host/lib/usrp/dboard/db_wbx.cpp +++ b/host/lib/usrp/dboard/db_wbx.cpp @@ -15,7 +15,7 @@ // along with this program. If not, see . // -static const bool wbx_debug = false; +static const bool wbx_debug = true; // Common IO Pins #define ANTSW_IO ((1 << 5)|(1 << 15)) // on UNIT_TX, 0 = TX, 1 = RX, on UNIT_RX 0 = main ant, 1 = RX2 @@ -147,8 +147,8 @@ static dboard_base::sptr make_wbx(dboard_base::ctor_args_t const& args){ } UHD_STATIC_BLOCK(reg_wbx_dboards){ - dboard_manager::register_dboard(0x0052, &make_wbx, "WBX NG RX"); - dboard_manager::register_dboard(0x0053, &make_wbx, "WBX NG TX"); + dboard_manager::register_dboard(0x0052, &make_wbx, "WBX RX"); + dboard_manager::register_dboard(0x0053, &make_wbx, "WBX TX"); } /*********************************************************************** @@ -167,6 +167,9 @@ wbx_xcvr::wbx_xcvr( //set the gpio directions this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TXIO_MASK); this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RXIO_MASK); + if (wbx_debug) std::cerr << boost::format( + "WBX GPIO Direction: RX: 0x%08x, TX: 0x%08x" + ) % RXIO_MASK % TXIO_MASK << std::endl; //set some default values set_rx_lo_freq((_freq_range.min + _freq_range.max)/2.0); @@ -203,6 +206,9 @@ void wbx_xcvr::update_atr(void){ //set the rx atr regs that change with antenna setting this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, _rx_pga0_attn_iobits | RX_POWER_UP | RX_MIXER_ENB | ((_rx_ant == "TX/RX")? ANT_TXRX : ANT_RX2)); + if (wbx_debug) std::cerr << boost::format( + "WBX RXONLY ATR REG: 0x%08x" + ) % (_rx_pga0_attn_iobits | RX_POWER_UP | RX_MIXER_ENB | ((_rx_ant == "TX/RX")? ANT_TXRX : ANT_RX2)) << std::endl; } void wbx_xcvr::set_rx_lo_freq(double freq){ @@ -311,7 +317,7 @@ double wbx_xcvr::set_lo_freq( } //use 8/9 prescaler for vco_freq > 3 GHz (pg.18 prescaler) - adf4350_regs_t::prescaler_t prescaler = vco_freq > 3e9 ? adf4350_regs_t::PRESCALER_4_5 : adf4350_regs_t::PRESCALER_8_9; + adf4350_regs_t::prescaler_t prescaler = vco_freq > 3e9 ? adf4350_regs_t::PRESCALER_8_9 : adf4350_regs_t::PRESCALER_4_5; /* * The goal here is to loop though possible R dividers, @@ -344,9 +350,9 @@ double wbx_xcvr::set_lo_freq( if (N < prescaler_to_min_int_div[prescaler]) continue; for(BS=1; BS <= 255; BS+=1){ - //keep the band select frequency at or below 125KHz + //keep the band select frequency at or below 100KHz //constraint on band select clock - if (pfd_freq/BS > 125e3) continue; + if (pfd_freq/BS > 100e3) continue; goto done_loop; } } done_loop: @@ -368,10 +374,10 @@ double wbx_xcvr::set_lo_freq( std::cerr << boost::format("WBX Intermediates: ref=%0.2f, outdiv=%f, fbdiv=%f") % (ref_freq*(1+int(D))/(R*(1+int(T)))) % double(RFdiv*2) % (double(FRAC)/double(MOD)) << std::endl; if (wbx_debug) std::cerr - << boost::format("WBX tune: R=%d, BS=%d, N=%d, FRAC=%d, MOD=%d, T=%d, D=%d, RFdiv=%d" - ) % R % BS % N % FRAC % MOD % T % D % RFdiv << std::endl + << boost::format("WBX tune: R=%d, BS=%d, N=%d, FRAC=%d, MOD=%d, T=%d, D=%d, RFdiv=%d, LD=%d" + ) % R % BS % N % FRAC % MOD % T % D % RFdiv % get_locked(unit)<< std::endl << boost::format("WBX Frequencies (MHz): REQ=%0.2f, ACT=%0.2f, VCO=%0.2f, PFD=%0.2f, BAND=%0.2f" - ) % (target_freq*2/1e6) % (actual_freq/1e6) % (vco_freq/1e6) % (pfd_freq/1e6) % (pfd_freq/BS/1e6) << std::endl; + ) % (target_freq/1e6) % (actual_freq/1e6) % (vco_freq/1e6) % (pfd_freq/1e6) % (pfd_freq/BS/1e6) << std::endl; //load the register values adf4350_regs_t regs; @@ -391,9 +397,12 @@ double wbx_xcvr::set_lo_freq( int addr; for(addr=5; addr>=0; addr--){ + if (wbx_debug) std::cerr << boost::format( + "WBX SPI Reg (0x%02x): 0x%08x" + ) % addr % regs.get_reg(addr) << std::endl; this->get_iface()->write_spi( unit, spi_config_t::EDGE_RISE, - regs.get_reg(addr), 24 + regs.get_reg(addr), 32 ); } -- cgit v1.2.3