From 167be5318376a4a431f18f9f7779cb9cdab6d8f8 Mon Sep 17 00:00:00 2001 From: Sugandha Gupta Date: Tue, 25 Sep 2018 15:27:11 -0700 Subject: e320: devtest: Reduce sample rate for 1G devtest The E320 default master clock rate is 16MHz, therefore we need to reduce the 2 channel receive rate to 8MHz in order to be able to meet the requested rate. --- host/tests/devtest/devtest_e320.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/tests/devtest') diff --git a/host/tests/devtest/devtest_e320.py b/host/tests/devtest/devtest_e320.py index 3d08a2521..04d240e94 100644 --- a/host/tests/devtest/devtest_e320.py +++ b/host/tests/devtest/devtest_e320.py @@ -23,7 +23,7 @@ uhd_benchmark_rate_test.tests = { 'duration': 1, 'direction': 'tx,rx', 'chan': '0,1', - 'rate': 12.5e6, + 'rate': 8e6, 'acceptable-underruns': 500, 'tx_buffer': (0.1*12.5e6)+32e6*8*1/32, # 32 MB DRAM for each channel (32 bit OTW format), 'rx_buffer': 0.1*12.5e6, -- cgit v1.2.3