From fc3f91e0cfb77e295673ac04d310ded65863c119 Mon Sep 17 00:00:00 2001 From: mattprost Date: Tue, 28 Jul 2020 13:29:38 -0500 Subject: twinrx: update synthesizer register values for improved rf performance Updated Register values for ADF5356: R2) Expand Frac2 to a 28-bit value for ADF5356 R6) Use negative bleed current for improved spurious performance R7) Set Fractional-N Lock Detect Precision to 12.0 ns because of bleed currents R8) Use magic number for reserved bits R9) Fix VCO Band Division calculation for ADF5356 RD) Expand Frac2 to a 28-bit value for ADF5356 Signed-off-by: mattprost --- host/lib/ic_reg_maps/gen_adf5356_regs.py | 6 ++-- host/lib/include/uhdlib/usrp/common/adf535x.hpp | 39 ++++++++++++++++++------- 2 files changed, 31 insertions(+), 14 deletions(-) (limited to 'host/lib') diff --git a/host/lib/ic_reg_maps/gen_adf5356_regs.py b/host/lib/ic_reg_maps/gen_adf5356_regs.py index 11662a67c..afa64220d 100755 --- a/host/lib/ic_reg_maps/gen_adf5356_regs.py +++ b/host/lib/ic_reg_maps/gen_adf5356_regs.py @@ -68,14 +68,14 @@ cp_bleed_current 6[13:20] 0 rf_divider_select 6[21:23] 0 div1, div2, div4, div8, div16, div32, div64 feedback_select 6[24] 0 divided, fundamental reg6_reserved2 6[25:28] 0xA -negative_bleed 6[29] 0 disabled, enabled +negative_bleed 6[29] 1 disabled, enabled gated_bleed 6[30] 0 disabled, enabled bleed_polarity 6[31] 0 negative, positive ######################################################################## ## address 7 ######################################################################## ld_mode 7[4] 0 frac_n, int_n -frac_n_ld_precision 7[5:6] 0 5ns, 6ns, 8ns, 12ns +frac_n_ld_precision 7[5:6] 0x3 5ns, 6ns, 8ns, 12ns loss_of_lock_mode 7[7] 0 disabled, enabled ld_cyc_count 7[8:9] 0 1024, 2048, 4096, 8192 reg7_reserved0 7[10:24] 0x0 @@ -86,7 +86,7 @@ reg7_reserved2 7[28:31] 0x0 ######################################################################## ## address 8 ######################################################################## -reg8_reserved0 8[4:31] 0x5559656 +reg8_reserved0 8[4:31] 0x102D042 ######################################################################## ## address 9 ######################################################################## diff --git a/host/lib/include/uhdlib/usrp/common/adf535x.hpp b/host/lib/include/uhdlib/usrp/common/adf535x.hpp index e8f4a9309..03efecc36 100644 --- a/host/lib/include/uhdlib/usrp/common/adf535x.hpp +++ b/host/lib/include/uhdlib/usrp/common/adf535x.hpp @@ -96,8 +96,10 @@ const double ADF535X_MIN_OUT_FREQ = (3.4e9 / 64); const double ADF535X_PHASE_RESYNC_TIME = 400e-6; const uint32_t ADF535X_MOD1 = 16777216; -const uint32_t ADF535X_MAX_MOD2 = 16383; -const uint32_t ADF535X_MAX_FRAC2 = 16383; +const uint32_t ADF5355_MAX_MOD2 = 16383; +const uint32_t ADF5355_MAX_FRAC2 = 16383; +const uint32_t ADF5356_MAX_MOD2 = 268435455; +const uint32_t ADF5356_MAX_FRAC2 = 268435455; // const uint16_t ADF535X_MIN_INT_PRESCALER_89 = 75; } // namespace @@ -205,7 +207,7 @@ public: //----------------------------------------------------------- // Set VCO band divider - _regs.vco_band_div = static_cast(ceil(_pfd_freq / 2.4e6)); + _regs.vco_band_div = _set_vco_band_div(_pfd_freq); //----------------------------------------------------------- // Set ADC delay (code from ADI driver) @@ -342,6 +344,7 @@ public: } protected: + uint8_t _set_vco_band_div(double); double _set_frequency(double, double, bool); uhd::meta_range_t _get_charge_pump_current_range(); void _commit(); @@ -360,6 +363,12 @@ private: // Members }; // ADF5355 Functions +template <> +inline uint8_t adf535x_impl::_set_vco_band_div(double pfd_freq) +{ + return static_cast(ceil(pfd_freq / 2.4e6)); +} + template <> inline double adf535x_impl::_set_frequency( double target_freq, double freq_resolution, bool flush) @@ -420,9 +429,9 @@ inline double adf535x_impl::_set_frequency( const double gcd = double( uhd::math::gcd(static_cast(_pfd_freq), static_cast(freq_resolution))); const auto MOD2 = static_cast( - std::min(floor(_pfd_freq / gcd), static_cast(ADF535X_MAX_MOD2))); + std::min(floor(_pfd_freq / gcd), static_cast(ADF5355_MAX_MOD2))); const auto FRAC2 = static_cast( - std::min(ceil(residue * MOD2), static_cast(ADF535X_MAX_FRAC2))); + std::min(ceil(residue * MOD2), static_cast(ADF5355_MAX_FRAC2))); const double coerced_vco_freq = _pfd_freq * (_fb_after_divider ? rf_divider : 1) @@ -491,6 +500,12 @@ inline void adf535x_impl::_commit() } // ADF5356 Functions +template <> +inline uint8_t adf535x_impl::_set_vco_band_div(double pfd_freq) +{ + return static_cast(ceil(pfd_freq / 1.6e6)); +} + template <> inline double adf535x_impl::_set_frequency( double target_freq, double freq_resolution, bool flush) @@ -550,10 +565,10 @@ inline double adf535x_impl::_set_frequency( const double gcd = double( uhd::math::gcd(static_cast(_pfd_freq), static_cast(freq_resolution))); - const auto MOD2 = static_cast( - std::min(floor(_pfd_freq / gcd), static_cast(ADF535X_MAX_MOD2))); - const auto FRAC2 = static_cast( - std::min(round(residue * MOD2), static_cast(ADF535X_MAX_FRAC2))); + const auto MOD2 = static_cast( + std::min(floor(_pfd_freq / gcd), static_cast(ADF5356_MAX_MOD2))); + const auto FRAC2 = static_cast( + std::min(round(residue * MOD2), static_cast(ADF5356_MAX_FRAC2))); const double coerced_vco_freq = _pfd_freq * (_fb_after_divider ? rf_divider : 1) @@ -575,8 +590,10 @@ inline double adf535x_impl::_set_frequency( /* Update registers */ _regs.int_16_bit = INT; _regs.frac1_24_bit = FRAC1; - _regs.frac2_msb = FRAC2; - _regs.mod2_msb = MOD2; + _regs.frac2_lsb = narrow_cast(FRAC2 & 0x3FFF); + _regs.mod2_lsb = narrow_cast(MOD2 & 0x3FFF); + _regs.frac2_msb = narrow_cast(FRAC2 >> 14); + _regs.mod2_msb = narrow_cast(MOD2 >> 14); _regs.phase_24_bit = 0; if (flush) -- cgit v1.2.3