From ed3be5607de7ea20f3ed1a5bfef4a060ade006be Mon Sep 17 00:00:00 2001
From: Paul David <paul.david@ettus.com>
Date: Thu, 29 Sep 2016 14:36:04 -0700
Subject: max2871: Added label for the bit region VAS_DLY - Also added a
 template specialization for enabling the VAS_DLY bit locations based on
 VAS_TEMP setting (aka retune)

---
 host/lib/usrp/common/max287x.hpp | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'host/lib/usrp')

diff --git a/host/lib/usrp/common/max287x.hpp b/host/lib/usrp/common/max287x.hpp
index 596d992e0..540f5207f 100644
--- a/host/lib/usrp/common/max287x.hpp
+++ b/host/lib/usrp/common/max287x.hpp
@@ -824,6 +824,13 @@ void max287x<max287x_regs_t>::set_auto_retune(bool enabled)
     _regs.retune = enabled ? max287x_regs_t::RETUNE_ENABLED : max287x_regs_t::RETUNE_DISABLED;
 }
 
+template <>
+inline void max287x<max2871_regs_t>::set_auto_retune(bool enabled)
+{
+    _regs.retune = enabled ? max2871_regs_t::RETUNE_ENABLED : max2871_regs_t::RETUNE_DISABLED;
+    _regs.vas_dly = enabled ? max2871_regs_t::VAS_DLY_ENABLED : max2871_regs_t::VAS_DLY_DISABLED;
+}
+
 template <typename max287x_regs_t>
 void max287x<max287x_regs_t>::set_clock_divider_mode(clock_divider_mode_t mode)
 {
-- 
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