From c8a2e4881f06212be7e10227220ebac33987143b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 6 Apr 2012 12:07:15 -0700 Subject: usrp: fix set_clock_config typo for external and mimo clock ref This is a typo in the set_clock_config implementation. However, the enum values are the same, so this would not cause a bug. Fixed although set_clock_config is a deprecated interface. --- host/lib/usrp/multi_usrp.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp') diff --git a/host/lib/usrp/multi_usrp.cpp b/host/lib/usrp/multi_usrp.cpp index 42c654e6b..93c0eada6 100644 --- a/host/lib/usrp/multi_usrp.cpp +++ b/host/lib/usrp/multi_usrp.cpp @@ -379,8 +379,8 @@ public: std::string clock_source; switch(clock_config.ref_source){ case clock_config_t::REF_INT: clock_source = "internal"; break; - case clock_config_t::PPS_SMA: clock_source = "external"; break; - case clock_config_t::PPS_MIMO: clock_source = "mimo"; break; + case clock_config_t::REF_SMA: clock_source = "external"; break; + case clock_config_t::REF_MIMO: clock_source = "mimo"; break; default: clock_source = "unknown"; } this->set_clock_source(clock_source, mboard); -- cgit v1.2.3 From 00c241844a62c22cac538316d507c524acc1c393 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 9 Apr 2012 14:28:25 -0700 Subject: dsp: clear register now overlaps with numchan register. This fixes the bug of unwanted clearing when setting format. --- host/lib/usrp/cores/rx_dsp_core_200.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'host/lib/usrp') diff --git a/host/lib/usrp/cores/rx_dsp_core_200.cpp b/host/lib/usrp/cores/rx_dsp_core_200.cpp index 4b60f111c..cf8db1927 100644 --- a/host/lib/usrp/cores/rx_dsp_core_200.cpp +++ b/host/lib/usrp/cores/rx_dsp_core_200.cpp @@ -38,13 +38,12 @@ #define REG_RX_CTRL_STREAM_CMD _ctrl_base + 0 #define REG_RX_CTRL_TIME_HI _ctrl_base + 4 #define REG_RX_CTRL_TIME_LO _ctrl_base + 8 -#define REG_RX_CTRL_CLEAR _ctrl_base + 12 +#define REG_RX_CTRL_FORMAT _ctrl_base + 12 #define REG_RX_CTRL_VRT_HDR _ctrl_base + 16 #define REG_RX_CTRL_VRT_SID _ctrl_base + 20 #define REG_RX_CTRL_VRT_TLR _ctrl_base + 24 #define REG_RX_CTRL_NSAMPS_PP _ctrl_base + 28 #define REG_RX_CTRL_NCHANNELS _ctrl_base + 32 -#define REG_RX_CTRL_FORMAT REG_RX_CTRL_CLEAR //re-use clear address template T ceil_log2(T num){ return std::ceil(std::log(num)/std::log(T(2))); @@ -78,8 +77,7 @@ public: } void clear(void){ - _iface->poke32(REG_RX_CTRL_CLEAR, 1); //reset - _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); + _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); //also reset _iface->poke32(REG_RX_CTRL_VRT_HDR, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer -- cgit v1.2.3