From ab068598b62b5c05dc56df0e2a2a54cc0b37cdf2 Mon Sep 17 00:00:00 2001 From: Thomas Tsou Date: Thu, 26 Aug 2010 18:42:29 -0700 Subject: usrp1: Fix DDC rate storage value and comments for multiple channel support --- host/lib/usrp/usrp1/dsp_impl.cpp | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'host/lib/usrp') diff --git a/host/lib/usrp/usrp1/dsp_impl.cpp b/host/lib/usrp/usrp1/dsp_impl.cpp index ab2eed91c..d5a88fa2d 100644 --- a/host/lib/usrp/usrp1/dsp_impl.cpp +++ b/host/lib/usrp/usrp1/dsp_impl.cpp @@ -78,13 +78,23 @@ void usrp1_impl::rx_dsp_set(const wax::obj &key, const wax::obj &val) switch(key.as()) { case DSP_PROP_FREQ_SHIFT: { double new_freq = val.as(); - _iface->poke32(FR_RX_FREQ_0, - -dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_master_clock_freq())); - _tx_dsp_freq = new_freq; + boost::uint32_t reg_word = dsp_type1::calc_cordic_word_and_update( + new_freq, _clock_ctrl->get_master_clock_freq()); + + //TODO TODO TODO TODO TODO TODO TODO TODO TODO + // + // Handle multiple receive channels / DDC's + // + //TODO TODO TODO TODO TODO TODO TODO TODO TODO + _iface->poke32(FR_RX_FREQ_0, reg_word); + _iface->poke32(FR_RX_FREQ_1, reg_word); + _iface->poke32(FR_RX_FREQ_2, reg_word); + _iface->poke32(FR_RX_FREQ_3, reg_word); + + _rx_dsp_freq = new_freq; return; } case DSP_PROP_HOST_RATE: { - //FIXME: Stop and resume streaming during set? unsigned int rate = _clock_ctrl->get_master_clock_freq() / val.as(); -- cgit v1.2.3