From 64990acea741768becafb3e9dee171274f23f9d9 Mon Sep 17 00:00:00 2001 From: Jonathon Pendlum Date: Fri, 24 Apr 2015 15:53:43 -0700 Subject: e300: Reduced AD9361's RX data delay to improve timing in FPGA capture interface --- host/lib/usrp/e300/e300_defaults.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/usrp') diff --git a/host/lib/usrp/e300/e300_defaults.hpp b/host/lib/usrp/e300/e300_defaults.hpp index 8fe8c3a05..537a0cf3e 100644 --- a/host/lib/usrp/e300/e300_defaults.hpp +++ b/host/lib/usrp/e300/e300_defaults.hpp @@ -70,7 +70,7 @@ public: digital_interface_delays_t get_digital_interface_timing() { digital_interface_delays_t delays; delays.rx_clk_delay = 0; - delays.rx_data_delay = 0xF; + delays.rx_data_delay = 0x8; delays.tx_clk_delay = 0; delays.tx_data_delay = 0xF; return delays; -- cgit v1.2.3