From 0336b6fb3500fe12326a8618e65c1f48f0a36f1c Mon Sep 17 00:00:00 2001
From: Nick Foster <nick@nerdnetworks.org>
Date: Fri, 10 Dec 2010 12:18:02 -0800
Subject: packet_router: added set_mimo_clock_delay to clock_ctrl.

Delay range is fixed right now to [0.444, 9.744]ns in 300ps increments
---
 host/lib/usrp/usrp2/clock_ctrl.cpp | 46 ++++++++++++++++++++++++++++++++++++++
 host/lib/usrp/usrp2/clock_ctrl.hpp |  8 +++++++
 2 files changed, 54 insertions(+)

(limited to 'host/lib/usrp')

diff --git a/host/lib/usrp/usrp2/clock_ctrl.cpp b/host/lib/usrp/usrp2/clock_ctrl.cpp
index 7dde88027..73331e594 100644
--- a/host/lib/usrp/usrp2/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp2/clock_ctrl.cpp
@@ -244,6 +244,52 @@ public:
     double get_master_clock_rate(void){
         return 100e6;
     }
+    
+    void set_mimo_clock_delay(boost::uint8_t delay) {
+        //delay is a 5-bit value (0-31) for fine control
+        //the equations below determine delay for a given ramp current, # of caps and fine delay register
+        //delay range:
+        //range_ns = 200*((caps+3)/i_ramp_ua)*1.3286
+        //offset (zero delay):
+        //offset_ns = 0.34 + (1600 - i_ramp_ua)*1e-4 + ((caps-1)/ramp)*6
+        //delay_ns = offset_ns + range_ns * delay / 31
+        
+        if(delay == 0) {
+            switch(clk_regs.exp) {
+            case 5:
+                _ad9510_regs.delay_control_out5 = 0;
+                break;
+            case 6:
+                _ad9510_regs.delay_control_out6 = 0;
+                break;
+            default:
+                break; //delay not supported on U2 rev 3
+            }
+        } else {
+            switch(clk_regs.exp) {
+            case 5:
+                _ad9510_regs.delay_control_out5 = 1;
+                _ad9510_regs.ramp_current_out5 = ad9510_regs_t::RAMP_CURRENT_OUT5_200UA;
+                _ad9510_regs.ramp_capacitor_out5 = ad9510_regs_t::RAMP_CAPACITOR_OUT5_4CAPS;
+                _ad9510_regs.delay_fine_adjust_out5 = delay;
+                this->write_reg(0x34);
+                this->write_reg(0x35);
+                this->write_reg(0x36);
+                break;
+            case 6:
+                _ad9510_regs.delay_control_out6 = 1;
+                _ad9510_regs.ramp_current_out6 = ad9510_regs_t::RAMP_CURRENT_OUT6_200UA;
+                _ad9510_regs.ramp_capacitor_out6 = ad9510_regs_t::RAMP_CAPACITOR_OUT6_4CAPS;
+                _ad9510_regs.delay_fine_adjust_out6 = delay;
+                this->write_reg(0x38);
+                this->write_reg(0x39);
+                this->write_reg(0x3A);
+                break;
+            default:
+                break;
+            }
+        }
+    }
 
 private:
     /*!
diff --git a/host/lib/usrp/usrp2/clock_ctrl.hpp b/host/lib/usrp/usrp2/clock_ctrl.hpp
index 10523fa6b..2ec347cac 100644
--- a/host/lib/usrp/usrp2/clock_ctrl.hpp
+++ b/host/lib/usrp/usrp2/clock_ctrl.hpp
@@ -95,6 +95,14 @@ public:
      * \param enb true to enable
      */
     virtual void enable_mimo_clock_out(bool enb) = 0;
+    
+    /*!
+     * Set the output delay of the mimo clock
+     * Used to synchronise daisy-chained USRPs over the MIMO cable
+     * Can also be used to adjust delay for uneven reference cable lengths
+     * \param delay in an arbitrary scaling
+     */
+    virtual void set_mimo_clock_delay(boost::uint8_t delay) = 0;
 
 };
 
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