From 135ff0a63c05a506e03a6badc1cb5378a76110af Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 23 Jan 2011 15:02:22 +0000 Subject: usrp-e100: changes to regs map for re-mapping of address space --- host/lib/usrp/usrp_e100/usrp_e100_regs.hpp | 83 ++++++++++++++++-------------- 1 file changed, 43 insertions(+), 40 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp index a57fe5171..05d27be11 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp @@ -17,7 +17,6 @@ // Slave pointers #define UE_REG_SLAVE(n) ((n)<<7) -#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) ///////////////////////////////////////////////////// // Slave 0 -- Misc Regs @@ -89,16 +88,6 @@ #define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric #define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric - -//////////////////////////////////////////////////// -// Slave 5 -- Settings Bus -// -// Output-only, no readback, 32 registers total -// Each register must be written 32 bits at a time -// First the address xxx_xx00 and then xxx_xx10 - -#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) - /////////////////////////////////////////////////// // Slave 6 -- ATR Controller // 16 regs @@ -124,47 +113,60 @@ #define UE_REG_RB_TIME_PPS_SECS UE_REG_RB_MUX_32_BASE + 8 #define UE_REG_RB_TIME_PPS_TICKS UE_REG_RB_MUX_32_BASE + 12 +//////////////////////////////////////////////////// +// Slave 8 -- Settings Bus +// +// Output-only, no readback, 64 registers total +// Each register must be written 64 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define UE_REG_SETTINGS_BASE_ADDR(n) (UE_REG_SLAVE(8) + (4*(n))) + ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// -#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) -#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} -#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate -#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic -#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits -#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) +#define UE_REG_DSP_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(16) + (4*(n))) +#define UE_REG_DSP_RX_FREQ UE_REG_DSP_RX_ADDR(0) +#define UE_REG_DSP_RX_SCALE_IQ UE_REG_DSP_RX_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_RX_DECIM_RATE UE_REG_DSP_RX_ADDR(2) // hb and decim rate +#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_DSP_RX_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_DSP_RX_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define UE_REG_DSP_RX_MUX UE_REG_DSP_RX_ADDR(5) /////////////////////////////////////////////////// // VITA RX CTRL regs /////////////////////////////////////////////////// +#define UE_REG_CTRL_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(0) + (4*(n))) // The following 3 are logically a single command register. // They are clocked into the underlying fifo when time_ticks is written. -#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) -#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) -#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) -#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun -#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter -#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. -#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) -#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) -#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources +#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) +#define UE_REG_CTRL_RX_TIME_SECS UE_REG_CTRL_RX_ADDR(1) +#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_CTRL_RX_ADDR(2) +#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_CTRL_RX_ADDR(3) // write anything to clear overrun +#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter +#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_CTRL_RX_ADDR(5) // word 1 of packet. +#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_CTRL_RX_ADDR(6) +#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_CTRL_RX_ADDR(7) +#define UE_REG_CTRL_RX_NCHANNELS UE_REG_CTRL_RX_ADDR(8) // 1 in basic case, up to 4 for vector sources ///////////////////////////////////////////////// // DSP TX Regs //////////////////////////////////////////////// -#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) -#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} -#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) -#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) -#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) +#define UE_REG_DSP_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(32) + (4*(n))) +#define UE_REG_DSP_TX_FREQ UE_REG_DSP_TX_ADDR(0) +#define UE_REG_DSP_TX_SCALE_IQ UE_REG_DSP_TX_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_TX_INTERP_RATE UE_REG_DSP_TX_ADDR(2) +#define UE_REG_DSP_TX_UNUSED UE_REG_DSP_TX_ADDR(3) +#define UE_REG_DSP_TX_MUX UE_REG_DSP_TX_ADDR(4) ///////////////////////////////////////////////// // VITA TX CTRL regs //////////////////////////////////////////////// -#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) -#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) -#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) -#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) +#define UE_REG_CTRL_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) +#define UE_REG_CTRL_TX_NCHANNELS UE_REG_CTRL_TX_ADDR(0) +#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_CTRL_TX_ADDR(1) +#define UE_REG_CTRL_TX_REPORT_SID UE_REG_CTRL_TX_ADDR(2) +#define UE_REG_CTRL_TX_POLICY UE_REG_CTRL_TX_ADDR(3) #define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) #define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) @@ -189,11 +191,12 @@ * * */ -#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS -#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS -#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above -#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) -#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) +#define UE_REG_TIME64_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(40) + (4*(n))) +#define UE_REG_TIME64_SECS UE_REG_TIME64_ADDR(0) // value to set absolute secs to on next PPS +#define UE_REG_TIME64_TICKS UE_REG_TIME64_ADDR(1) // value to set absolute ticks to on next PPS +#define UE_REG_TIME64_FLAGS UE_REG_TIME64_ADDR(2) // flags - see chart above +#define UE_REG_TIME64_IMM UE_REG_TIME64_ADDR(3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_TPS UE_REG_TIME64_ADDR(4) // clock ticks per second (counter rollover) //pps flags (see above) #define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) -- cgit v1.2.3 From 3db02acdfd44b22c05eaafe66e751f8fbfb29dcd Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 25 Jan 2011 14:13:21 -0800 Subject: usrp-e100: added misc test register 32 bits --- host/lib/usrp/usrp_e100/usrp_e100_regs.hpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp index 05d27be11..7dc3a4ba8 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp @@ -112,6 +112,7 @@ #define UE_REG_RB_TIME_NOW_TICKS UE_REG_RB_MUX_32_BASE + 4 #define UE_REG_RB_TIME_PPS_SECS UE_REG_RB_MUX_32_BASE + 8 #define UE_REG_RB_TIME_PPS_TICKS UE_REG_RB_MUX_32_BASE + 12 +#define UE_REG_RB_MISC_TEST32 UE_REG_RB_MUX_32_BASE + 16 //////////////////////////////////////////////////// // Slave 8 -- Settings Bus @@ -122,6 +123,8 @@ #define UE_REG_SETTINGS_BASE_ADDR(n) (UE_REG_SLAVE(8) + (4*(n))) +#define UE_REG_SR_MISC_TEST32 UE_REG_SETTINGS_BASE_ADDR(52) + ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// -- cgit v1.2.3 From f393d6fd8d0c1bef33a3f7346867d6a7e103df19 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 29 Jan 2011 16:11:21 +0000 Subject: usrp-e100: so far internal vco code works w/ 64mhz --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 195 ++++++++++++++++++++++----------- 1 file changed, 133 insertions(+), 62 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 4048218f2..5fd0466d8 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010 Ettus Research LLC +// Copyright 2010-2011 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -18,17 +18,27 @@ #include "clock_ctrl.hpp" #include "ad9522_regs.hpp" #include -#include #include #include "usrp_e100_regs.hpp" //spi slave constants #include #include #include +#include +#include #include #include using namespace uhd; +/*********************************************************************** + * Constants + **********************************************************************/ +static const bool ENABLE_THE_TEST_CLOCK_OUT = true; +static const double REFERENCE_INPUT_RATE = 10e6; + +/*********************************************************************** + * Helpers + **********************************************************************/ template static void set_clock_divider( size_t divider, div_type &low, div_type &high, bypass_type &bypass ){ @@ -41,13 +51,13 @@ template static void set_clock_divider * Clock rate calculation stuff: * Using the internal VCO between 1400 and 1800 MHz **********************************************************************/ -struct clock_settings_type{ - size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, clk_divider; +struct clock_settings_type : boost::totally_ordered{ + size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider; size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} - double get_ref_rate(void) const{return 10e6 * ref_clock_doubler;} + double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;} double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();} - double get_clk_rate(void) const{return get_vco_rate()/vco_divider;} - double get_out_rate(void) const{return get_clk_rate()/clk_divider;} + double get_chan_rate(void) const{return get_vco_rate()/vco_divider;} + double get_out_rate(void) const{return get_chan_rate()/chan_divider;} std::string to_pp_string(void) const{ return str(boost::format( " r_counter: %d\n" @@ -55,9 +65,9 @@ struct clock_settings_type{ " b_counter: %d\n" " prescaler: %d\n" " vco_divider: %d\n" - " clk_divider: %d\n" + " chan_divider: %d\n" " vco_rate: %fMHz\n" - " clk_rate: %fMHz\n" + " chan_rate: %fMHz\n" " out_rate: %fMHz\n" ) % r_counter @@ -65,53 +75,53 @@ struct clock_settings_type{ % b_counter % prescaler % vco_divider - % clk_divider + % chan_divider % (get_vco_rate()/1e6) - % (get_clk_rate()/1e6) + % (get_chan_rate()/1e6) % (get_out_rate()/1e6) ); } }; -UHD_SINGLETON_FCN(std::vector, get_clock_settings); +bool operator<(const clock_settings_type &lhs, const clock_settings_type &rhs){ + if (lhs.get_out_rate() != rhs.get_out_rate()) //sort small to large out rates + return lhs.get_out_rate() < rhs.get_out_rate(); + + if (lhs.r_counter != rhs.r_counter) //sort small to large r dividers + return lhs.r_counter < rhs.r_counter; + + if (lhs.get_vco_rate() != rhs.get_vco_rate()) //sort large to small vco rates + return lhs.get_vco_rate() > rhs.get_vco_rate(); + + return false; //whatever case +} + +static std::vector _get_clock_settings(void){ + std::vector clock_settings; -UHD_STATIC_BLOCK(libuhd_usrp_e100_reg_clock_rates){ clock_settings_type cs; cs.ref_clock_doubler = 2; //always doubling cs.prescaler = 8; //set to 8 when input is under 2400 MHz - for (cs.r_counter = 1; cs.r_counter <= 1; cs.r_counter++){ + for (cs.r_counter = 1; cs.r_counter <= 3; cs.r_counter++){ for (cs.b_counter = 3; cs.b_counter <= 10; cs.b_counter++){ for (cs.a_counter = 0; cs.a_counter <= 10; cs.a_counter++){ for (cs.vco_divider = 2; cs.vco_divider <= 6; cs.vco_divider++){ - for (cs.clk_divider = 1; cs.clk_divider <= 32; cs.clk_divider++){ + for (cs.chan_divider = 1; cs.chan_divider <= 32; cs.chan_divider++){ if (cs.get_vco_rate() > 1800e6) continue; if (cs.get_vco_rate() < 1400e6) continue; if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface - //std::cout << (cs.get_out_rate()/1e6) << std::endl; - get_clock_settings().push_back(cs); + clock_settings.push_back(cs); }}}}} -} - -/*********************************************************************** - * Constants - **********************************************************************/ -static const bool enable_test_clock = false; -static const size_t ref_clock_doubler = 2; //enabled below -static const double ref_clock_rate = 10e6 * ref_clock_doubler; - -static const size_t r_counter = 1; -static const size_t a_counter = 0; -static const size_t b_counter = 20 / ref_clock_doubler; -static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz -static const size_t vco_divider = 5; //set below with enum -static const size_t n_counter = prescaler * b_counter + a_counter; -static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz -static const double master_clock_rate = vco_clock_rate/vco_divider; + std::sort(clock_settings.begin(), clock_settings.end()); + return clock_settings; +} -static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); -static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); +static std::vector &get_clock_settings(void){ + static std::vector clock_settings = _get_clock_settings(); + return clock_settings; +} /*********************************************************************** * Clock Control Implementation @@ -120,6 +130,8 @@ class usrp_e100_clock_ctrl_impl : public usrp_e100_clock_ctrl{ public: usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface){ _iface = iface; + _chan_rate = 0.0; + _out_rate = 0.0; //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work @@ -134,16 +146,27 @@ public: this->set_fpga_clock_rate(64e6); //initialize to something + this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } ~usrp_e100_clock_ctrl_impl(void){ + this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } + /*********************************************************************** + * Clock rate control: + * - set clock rate w/ internal VCO + * - set clock rate w/ external VCXO + **********************************************************************/ void set_clock_settings_with_internal_vco(const clock_settings_type &cs){ + //set the rates to private variables so the implementation knows! + _chan_rate = cs.get_chan_rate(); + _out_rate = cs.get_out_rate(); + _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0; _ad9522_regs.set_r_counter(cs.r_counter); @@ -156,6 +179,7 @@ public: _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.vco_calibration_now = 1; //calibrate it! + _ad9522_regs.bypass_vco_divider = 0; switch(cs.vco_divider){ case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break; @@ -168,7 +192,7 @@ public: //setup fpga master clock _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - set_clock_divider(cs.clk_divider, + set_clock_divider(cs.chan_divider, _ad9522_regs.divider0_low_cycles, _ad9522_regs.divider0_high_cycles, _ad9522_regs.divider0_bypass @@ -176,44 +200,58 @@ public: //setup codec clock _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - set_clock_divider(cs.clk_divider, + set_clock_divider(cs.chan_divider, _ad9522_regs.divider1_low_cycles, _ad9522_regs.divider1_high_cycles, _ad9522_regs.divider1_bypass ); - //setup test clock (same divider as codec clock) - _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; - _ad9522_regs.out4_cmos_configuration = (enable_test_clock)? - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + this->send_all_regs(); + } - //setup a list of register ranges to write - typedef std::pair range_t; - static const std::vector ranges = boost::assign::list_of - (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) - (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) - (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) - ; + void set_clock_settings_with_external_vcxo(double rate){ + //set the rates to private variables so the implementation knows! + _chan_rate = rate; + _out_rate = rate; - //write initial register values and latch/update - BOOST_FOREACH(const range_t &range, ranges){ - for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ - this->send_reg(addr); - } - } - this->latch_regs(); + _ad9522_regs.enable_clock_doubler = 1; + + //bypass prescalers and counters == 1 + _ad9522_regs.set_r_counter(1); + _ad9522_regs.a_counter = 0; + _ad9522_regs.set_b_counter(1); + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; + + //setup external vcxo + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_ASYNC; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + _ad9522_regs.bypass_vco_divider = 1; + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + _ad9522_regs.divider0_bypass = 1; + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + _ad9522_regs.divider1_bypass = 1; + + this->send_all_regs(); } void set_fpga_clock_rate(double rate){ + if (_out_rate == rate) return; + if (rate == 61.44e6){ - //TODO special settings for external VCXO + set_clock_settings_with_external_vcxo(rate); } else{ BOOST_FOREACH(const clock_settings_type &cs, get_clock_settings()){ + //std::cout << cs.to_pp_string() << std::endl; if (rate != cs.get_out_rate()) continue; std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; set_clock_settings_with_internal_vco(cs); + return; //done here, exits loop } throw std::runtime_error(str(boost::format( "USRP-E100 clock control: could not find settings for clock rate %fMHz" @@ -222,7 +260,20 @@ public: } double get_fpga_clock_rate(void){ - return master_clock_rate/fpga_clock_divider; + return this->_out_rate; + } + + /*********************************************************************** + * Special test clock output + **********************************************************************/ + void enable_test_clock(bool enb){ + //setup test clock (same divider as codec clock) + _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; + _ad9522_regs.out4_cmos_configuration = (enb)? + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F0); + this->latch_regs(); } /*********************************************************************** @@ -240,13 +291,13 @@ public: std::vector get_rx_dboard_clock_rates(void){ std::vector rates; for(size_t div = 1; div <= 16+16; div++) - rates.push_back(master_clock_rate/div); + rates.push_back(this->_chan_rate/div); return rates; } void set_rx_dboard_clock_rate(double rate){ assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); - size_t divider = size_t(master_clock_rate/rate); + size_t divider = size_t(this->_chan_rate/rate); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider3_low_cycles, @@ -276,7 +327,7 @@ public: void set_tx_dboard_clock_rate(double rate){ assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); - size_t divider = size_t(master_clock_rate/rate); + size_t divider = size_t(this->_chan_rate/rate); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider2_low_cycles, @@ -317,6 +368,8 @@ public: private: usrp_e100_iface::sptr _iface; ad9522_regs_t _ad9522_regs; + double _out_rate; //rate at the fpga and codec + double _chan_rate; //rate before final dividers void latch_regs(void){ _ad9522_regs.io_update = 1; @@ -332,6 +385,24 @@ private: reg, 24, false /*no rb*/ ); } + + void send_all_regs(void){ + //setup a list of register ranges to write + typedef std::pair range_t; + static const std::vector ranges = boost::assign::list_of + (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) + (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) + (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) + ; + + //write initial register values and latch/update + BOOST_FOREACH(const range_t &range, ranges){ + for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ + this->send_reg(addr); + } + } + this->latch_regs(); + } }; /*********************************************************************** -- cgit v1.2.3 From ef6331f622aacadf233369637e08bfb7f2e6995a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 29 Jan 2011 20:29:12 +0000 Subject: usrp-e100: working clock control 61.44, 52mhz --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 5fd0466d8..e2c4889bc 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -33,8 +33,9 @@ using namespace uhd; /*********************************************************************** * Constants **********************************************************************/ -static const bool ENABLE_THE_TEST_CLOCK_OUT = true; +static const bool ENABLE_THE_TEST_OUT = false; static const double REFERENCE_INPUT_RATE = 10e6; +static const double DEFAULT_OUTPUT_RATE = 64e6; /*********************************************************************** * Helpers @@ -138,21 +139,22 @@ public: _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin - _ad9522_regs.status_pin_control = 0x1; //n divider + _ad9522_regs.status_pin_control = 0x2; //r divider _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 + _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_255CYC; this->use_internal_ref(); - this->set_fpga_clock_rate(64e6); //initialize to something + this->set_fpga_clock_rate(DEFAULT_OUTPUT_RATE); //initialize to something - this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); + this->enable_test_clock(ENABLE_THE_TEST_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } ~usrp_e100_clock_ctrl_impl(void){ - this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); + this->enable_test_clock(ENABLE_THE_TEST_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } @@ -217,13 +219,13 @@ public: _ad9522_regs.enable_clock_doubler = 1; //bypass prescalers and counters == 1 - _ad9522_regs.set_r_counter(1); + _ad9522_regs.set_r_counter(125); _ad9522_regs.a_counter = 0; - _ad9522_regs.set_b_counter(1); + _ad9522_regs.set_b_counter(384); _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; //setup external vcxo - _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_ASYNC; + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.bypass_vco_divider = 1; _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL; -- cgit v1.2.3 From 572a64f0acb459583abfccbc8288158822fa2f77 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 29 Jan 2011 21:03:29 +0000 Subject: usrp-e100: clock control use boost math gcd for divider calculation --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index e2c4889bc..dd7f8507b 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -24,6 +24,7 @@ #include #include #include +#include //gcd #include #include #include @@ -216,12 +217,14 @@ public: _chan_rate = rate; _out_rate = rate; - _ad9522_regs.enable_clock_doubler = 1; + _ad9522_regs.enable_clock_doubler = 1; //doubler always on + const double ref_rate = REFERENCE_INPUT_RATE*2; - //bypass prescalers and counters == 1 - _ad9522_regs.set_r_counter(125); + //bypass prescaler such that N = B + long gcd = boost::math::gcd(long(ref_rate), long(rate)); + _ad9522_regs.set_r_counter(int(ref_rate/gcd)); _ad9522_regs.a_counter = 0; - _ad9522_regs.set_b_counter(384); + _ad9522_regs.set_b_counter(int(rate/gcd)); _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; //setup external vcxo -- cgit v1.2.3 From 8aea3fb21dda08bcb64ff00a07de448615818a98 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 30 Jan 2011 20:39:26 -0800 Subject: usrp-e100: work on clock control --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 123 +++++++++++++++++++++++++++------ host/lib/usrp/usrp_e100/clock_ctrl.hpp | 7 ++ 2 files changed, 108 insertions(+), 22 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 1fb1a7125..4048218f2 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -18,10 +18,12 @@ #include "clock_ctrl.hpp" #include "ad9522_regs.hpp" #include +#include #include #include "usrp_e100_regs.hpp" //spi slave constants #include #include +#include #include #include @@ -35,6 +37,62 @@ template static void set_clock_divider bypass = (divider == 1)? 1 : 0; } +/*********************************************************************** + * Clock rate calculation stuff: + * Using the internal VCO between 1400 and 1800 MHz + **********************************************************************/ +struct clock_settings_type{ + size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, clk_divider; + size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} + double get_ref_rate(void) const{return 10e6 * ref_clock_doubler;} + double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();} + double get_clk_rate(void) const{return get_vco_rate()/vco_divider;} + double get_out_rate(void) const{return get_clk_rate()/clk_divider;} + std::string to_pp_string(void) const{ + return str(boost::format( + " r_counter: %d\n" + " a_counter: %d\n" + " b_counter: %d\n" + " prescaler: %d\n" + " vco_divider: %d\n" + " clk_divider: %d\n" + " vco_rate: %fMHz\n" + " clk_rate: %fMHz\n" + " out_rate: %fMHz\n" + ) + % r_counter + % a_counter + % b_counter + % prescaler + % vco_divider + % clk_divider + % (get_vco_rate()/1e6) + % (get_clk_rate()/1e6) + % (get_out_rate()/1e6) + ); + } +}; + +UHD_SINGLETON_FCN(std::vector, get_clock_settings); + +UHD_STATIC_BLOCK(libuhd_usrp_e100_reg_clock_rates){ + clock_settings_type cs; + cs.ref_clock_doubler = 2; //always doubling + cs.prescaler = 8; //set to 8 when input is under 2400 MHz + + for (cs.r_counter = 1; cs.r_counter <= 1; cs.r_counter++){ + for (cs.b_counter = 3; cs.b_counter <= 10; cs.b_counter++){ + for (cs.a_counter = 0; cs.a_counter <= 10; cs.a_counter++){ + for (cs.vco_divider = 2; cs.vco_divider <= 6; cs.vco_divider++){ + for (cs.clk_divider = 1; cs.clk_divider <= 32; cs.clk_divider++){ + if (cs.get_vco_rate() > 1800e6) continue; + if (cs.get_vco_rate() < 1400e6) continue; + if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface + //std::cout << (cs.get_out_rate()/1e6) << std::endl; + get_clock_settings().push_back(cs); + }}}}} +} + /*********************************************************************** * Constants **********************************************************************/ @@ -72,25 +130,45 @@ public: _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 - _ad9522_regs.enable_ref2 = 1; - _ad9522_regs.enable_ref1 = 0; - _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + this->use_internal_ref(); - _ad9522_regs.set_r_counter(r_counter); - _ad9522_regs.a_counter = a_counter; - _ad9522_regs.set_b_counter(b_counter); + this->set_fpga_clock_rate(64e6); //initialize to something + + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + ~usrp_e100_clock_ctrl_impl(void){ + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + void set_clock_settings_with_internal_vco(const clock_settings_type &cs){ + _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0; + + _ad9522_regs.set_r_counter(cs.r_counter); + _ad9522_regs.a_counter = cs.a_counter; + _ad9522_regs.set_b_counter(cs.b_counter); + UHD_ASSERT_THROW(cs.prescaler == 8); //assumes this below: _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.vco_calibration_now = 1; //calibrate it! - _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; + switch(cs.vco_divider){ + case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; + case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break; + case 3: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV3; break; + case 4: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV4; break; + case 5: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; break; + case 6: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV6; break; + } _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; //setup fpga master clock _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - set_clock_divider(fpga_clock_divider, + set_clock_divider(cs.clk_divider, _ad9522_regs.divider0_low_cycles, _ad9522_regs.divider0_high_cycles, _ad9522_regs.divider0_bypass @@ -98,7 +176,7 @@ public: //setup codec clock _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - set_clock_divider(codec_clock_divider, + set_clock_divider(cs.clk_divider, _ad9522_regs.divider1_low_cycles, _ad9522_regs.divider1_high_cycles, _ad9522_regs.divider1_bypass @@ -125,21 +203,22 @@ public: } } this->latch_regs(); - //test read: - //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b); - //boost::uint32_t result = _iface->transact_spi( - // UE_SPI_SS_AD9522, - // spi_config_t::EDGE_RISE, - // reg, 24, true /*no*/ - //); - //std::cout << "result " << std::hex << result << std::endl; - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); } - ~usrp_e100_clock_ctrl_impl(void){ - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); + void set_fpga_clock_rate(double rate){ + if (rate == 61.44e6){ + //TODO special settings for external VCXO + } + else{ + BOOST_FOREACH(const clock_settings_type &cs, get_clock_settings()){ + if (rate != cs.get_out_rate()) continue; + std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; + set_clock_settings_with_internal_vco(cs); + } + throw std::runtime_error(str(boost::format( + "USRP-E100 clock control: could not find settings for clock rate %fMHz" + ) % (rate/1e6))); + } } double get_fpga_clock_rate(void){ diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp index d613d1473..1f9960ce4 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp @@ -39,6 +39,13 @@ public: */ static sptr make(usrp_e100_iface::sptr iface); + /*! + * Set the rate of the fpga clock line. + * Throws if rate is not valid. + * \param rate the new rate in Hz + */ + virtual void set_fpga_clock_rate(double rate) = 0; + /*! * Get the rate of the fpga clock line. * \return the fpga clock rate in Hz -- cgit v1.2.3 From cd45fb6be615a6f133e2c62a46f7c5eba76f72c1 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 31 Jan 2011 09:59:44 -0800 Subject: usrp-e100: remove unused clock control constants, enb test clock --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 4048218f2..a8d88fa42 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -96,22 +96,7 @@ UHD_STATIC_BLOCK(libuhd_usrp_e100_reg_clock_rates){ /*********************************************************************** * Constants **********************************************************************/ -static const bool enable_test_clock = false; -static const size_t ref_clock_doubler = 2; //enabled below -static const double ref_clock_rate = 10e6 * ref_clock_doubler; - -static const size_t r_counter = 1; -static const size_t a_counter = 0; -static const size_t b_counter = 20 / ref_clock_doubler; -static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz -static const size_t vco_divider = 5; //set below with enum - -static const size_t n_counter = prescaler * b_counter + a_counter; -static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz -static const double master_clock_rate = vco_clock_rate/vco_divider; - -static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); -static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); +static const bool enable_test_clock = true; /*********************************************************************** * Clock Control Implementation -- cgit v1.2.3 From 4afdcd180e5ee6b93fefe2fb07b071452fb7ef3f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 30 Jan 2011 15:04:15 +0000 Subject: usrp-e100: tweaks to clock control and setting from api --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 12 +++++++----- host/lib/usrp/usrp_e100/mboard_impl.cpp | 8 ++++++++ 2 files changed, 15 insertions(+), 5 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 05a27c38b..ef5e9b5ec 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -115,12 +115,15 @@ static std::vector _get_clock_settings(void){ if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface clock_settings.push_back(cs); }}}}} + + std::sort(clock_settings.begin(), clock_settings.end()); + return clock_settings; } -/*********************************************************************** - * Constants - **********************************************************************/ -static const bool enable_test_clock = true; +static std::vector &get_clock_settings(void){ + static std::vector clock_settings = _get_clock_settings(); + return clock_settings; +} /*********************************************************************** * Clock Control Implementation @@ -135,7 +138,6 @@ public: //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; - _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin _ad9522_regs.status_pin_control = 0x2; //r divider _ad9522_regs.ld_pin_control = 0x00; //dld diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index f52d2e6fb..0e08cd435 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -152,6 +152,10 @@ void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; } + case MBOARD_PROP_CLOCK_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -211,6 +215,10 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){ update_clock_config(); return; + case MBOARD_PROP_CLOCK_RATE: + _clock_ctrl->set_fpga_clock_rate(val.as()); + return; + default: UHD_THROW_PROP_SET_ERROR(); } } -- cgit v1.2.3 From 7b03f4144a0dc7a1e745ac43a3997b0eab7042c0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 30 Jan 2011 22:10:49 +0000 Subject: usrp-e100: work on clock control added vco calibration routine and readback to check for calibrated changed the counters/dividers calculation to be event driven and more mathematically calculated. --- host/lib/ic_reg_maps/gen_ad9522_regs.py | 8 ++ host/lib/usrp/usrp_e100/clock_ctrl.cpp | 151 +++++++++++++++++++++----------- 2 files changed, 106 insertions(+), 53 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py index a5debe568..86605c34a 100755 --- a/host/lib/ic_reg_maps/gen_ad9522_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py @@ -80,6 +80,14 @@ external_zero_delay_fcds 0x01E[4:3] 0 enable_external_zero_delay 0x01E[2] 0 enable_zero_delay 0x01E[1] 0 ######################################################################## +vco_calibration_finished 0x01F[6] 0 +holdover_active 0x01F[5] 0 +ref2_selected 0x01F[4] 0 +vco_freq_gt_thresh 0x01F[3] 0 +ref2_freq_gt_thresh 0x01F[2] 0 +ref1_freq_gt_thresh 0x01F[1] 0 +digital_lock_detect 0x01F[0] 0 +######################################################################## #for $i in range(12) #set $addr = ($i + 0x0F0) out$(i)_format $(addr)[7] 0 lvds, cmos diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index ef5e9b5ec..36ab1a8be 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include //gcd #include #include @@ -34,7 +34,8 @@ using namespace uhd; /*********************************************************************** * Constants **********************************************************************/ -static const bool ENABLE_THE_TEST_OUT = false; +static const bool CLOCK_SETTINGS_DEBUG = false; +static const bool ENABLE_THE_TEST_OUT = true; static const double REFERENCE_INPUT_RATE = 10e6; static const double DEFAULT_OUTPUT_RATE = 64e6; @@ -53,7 +54,7 @@ template static void set_clock_divider * Clock rate calculation stuff: * Using the internal VCO between 1400 and 1800 MHz **********************************************************************/ -struct clock_settings_type : boost::totally_ordered{ +struct clock_settings_type{ size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider; size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;} @@ -85,44 +86,78 @@ struct clock_settings_type : boost::totally_ordered{ } }; -bool operator<(const clock_settings_type &lhs, const clock_settings_type &rhs){ - if (lhs.get_out_rate() != rhs.get_out_rate()) //sort small to large out rates - return lhs.get_out_rate() < rhs.get_out_rate(); - - if (lhs.r_counter != rhs.r_counter) //sort small to large r dividers - return lhs.r_counter < rhs.r_counter; - - if (lhs.get_vco_rate() != rhs.get_vco_rate()) //sort large to small vco rates - return lhs.get_vco_rate() > rhs.get_vco_rate(); - - return false; //whatever case +//! gives the greatest divisor of num between 1 and max inclusive +template static inline T greatest_divisor(T num, T max){ + for (T i = max; i > 1; i--) if (num%i == 0) return i; return 1; } -static std::vector _get_clock_settings(void){ - std::vector clock_settings; +//! gives the least divisor of num between min and num exclusive +template static inline T least_divisor(T num, T min){ + for (T i = min; i < num; i++) if (num%i == 0) return i; return 1; +} +static clock_settings_type get_clock_settings(double rate){ clock_settings_type cs; cs.ref_clock_doubler = 2; //always doubling cs.prescaler = 8; //set to 8 when input is under 2400 MHz - for (cs.r_counter = 1; cs.r_counter <= 3; cs.r_counter++){ - for (cs.b_counter = 3; cs.b_counter <= 10; cs.b_counter++){ - for (cs.a_counter = 0; cs.a_counter <= 10; cs.a_counter++){ - for (cs.vco_divider = 2; cs.vco_divider <= 6; cs.vco_divider++){ - for (cs.chan_divider = 1; cs.chan_divider <= 32; cs.chan_divider++){ - if (cs.get_vco_rate() > 1800e6) continue; - if (cs.get_vco_rate() < 1400e6) continue; - if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface - clock_settings.push_back(cs); - }}}}} - - std::sort(clock_settings.begin(), clock_settings.end()); - return clock_settings; -} + //basic formulas used below: + //out_rate*X = ref_rate*Y + //X = i*ref_rate/gcd + //Y = i*out_rate/gcd + //X = chan_div * vco_div * R + //Y = P*B + A + + const boost::uint64_t out_rate = boost::uint64_t(rate); + const boost::uint64_t ref_rate = boost::uint64_t(cs.get_ref_rate()); + const size_t gcd = size_t(boost::math::gcd(ref_rate, out_rate)); + + for (size_t i = 1; i <= 100; i++){ + const size_t X = i*ref_rate/gcd; + const size_t Y = i*out_rate/gcd; + + //determine chan_div, vco_div, and r_div + //and fill in that order of preference + cs.chan_divider = greatest_divisor(X, 32); + cs.vco_divider = greatest_divisor(X/cs.chan_divider, 6); + cs.r_counter = X/cs.chan_divider/cs.vco_divider; + + //avoid a vco divider of 1 (if possible) + if (cs.vco_divider == 1){ + cs.vco_divider = least_divisor(cs.chan_divider, 2); + cs.chan_divider /= cs.vco_divider; + } + + //determine A and B (P is fixed) + cs.b_counter = Y/cs.prescaler; + cs.a_counter = Y - cs.b_counter*cs.prescaler; + + if (CLOCK_SETTINGS_DEBUG){ + std::cout << "X " << X << std::endl; + std::cout << "Y " << Y << std::endl; + std::cout << cs.to_pp_string() << std::endl; + } + + //filter limits on the counters + if (cs.vco_divider == 1) continue; + if (cs.r_counter >= (1<<14)) continue; + if (cs.b_counter == 2) continue; + if (cs.b_counter == 1 and cs.a_counter != 0) continue; + if (cs.b_counter >= (1<<13)) continue; + if (cs.a_counter >= (1<<6)) continue; + + //check the bounds on the vco + static const double vco_bound_pad = 100e6; + if (cs.get_vco_rate() > (1800e6 - vco_bound_pad)) continue; + if (cs.get_vco_rate() < (1400e6 + vco_bound_pad)) continue; + + std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; + return cs; + } -static std::vector &get_clock_settings(void){ - static std::vector clock_settings = _get_clock_settings(); - return clock_settings; + throw std::runtime_error(str(boost::format( + "USRP-E100 clock control: could not calculate settings for clock rate %fMHz" + ) % (rate/1e6))); } /*********************************************************************** @@ -139,10 +174,10 @@ public: //Note: out0 should already be clocking the FPGA or this isnt going to work _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin - _ad9522_regs.status_pin_control = 0x2; //r divider + _ad9522_regs.status_pin_control = 0x1; //n divider _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 - _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_255CYC; + _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; this->use_internal_ref(); @@ -164,7 +199,9 @@ public: * - set clock rate w/ internal VCO * - set clock rate w/ external VCXO **********************************************************************/ - void set_clock_settings_with_internal_vco(const clock_settings_type &cs){ + void set_clock_settings_with_internal_vco(double rate){ + const clock_settings_type cs = get_clock_settings(rate); + //set the rates to private variables so the implementation knows! _chan_rate = cs.get_chan_rate(); _out_rate = cs.get_out_rate(); @@ -180,7 +217,6 @@ public: _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; - _ad9522_regs.vco_calibration_now = 1; //calibrate it! _ad9522_regs.bypass_vco_divider = 0; switch(cs.vco_divider){ case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; @@ -209,6 +245,7 @@ public: ); this->send_all_regs(); + calibrate_now(); } void set_clock_settings_with_external_vcxo(double rate){ @@ -245,22 +282,8 @@ public: void set_fpga_clock_rate(double rate){ if (_out_rate == rate) return; - - if (rate == 61.44e6){ - set_clock_settings_with_external_vcxo(rate); - } - else{ - BOOST_FOREACH(const clock_settings_type &cs, get_clock_settings()){ - //std::cout << cs.to_pp_string() << std::endl; - if (rate != cs.get_out_rate()) continue; - std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; - set_clock_settings_with_internal_vco(cs); - return; //done here, exits loop - } - throw std::runtime_error(str(boost::format( - "USRP-E100 clock control: could not find settings for clock rate %fMHz" - ) % (rate/1e6))); - } + if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate); + else set_clock_settings_with_internal_vco(rate); } double get_fpga_clock_rate(void){ @@ -390,6 +413,28 @@ private: ); } + void calibrate_now(void){ + //vco calibration routine: + _ad9522_regs.vco_calibration_now = 0; + this->send_reg(0x18); + this->latch_regs(); + _ad9522_regs.vco_calibration_now = 1; + this->send_reg(0x18); + this->latch_regs(); + //wait for calibration done: + static const boost::uint8_t addr = 0x01F; + for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::uint32_t reg = _iface->transact_spi( + UE_SPI_SS_AD9522, spi_config_t::EDGE_RISE, + _ad9522_regs.get_read_reg(addr), 24, true /*rb*/ + ); + _ad9522_regs.set_reg(addr, reg); + if (_ad9522_regs.vco_calibration_finished) return; + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + } + std::cerr << "USRP-E100 clock control: VCO calibration timeout" << std::endl; + } + void send_all_regs(void){ //setup a list of register ranges to write typedef std::pair range_t; -- cgit v1.2.3 From 2cb6092ddfcf5f3881faa455566d4f332b01d0ac Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 31 Jan 2011 20:26:45 +0000 Subject: usrp-e100: combined clkconfig and fpga downloader into usrp-e-utility, simplified code --- host/examples/rx_timed_samples.cpp | 9 +- host/lib/usrp/usrp_e100/CMakeLists.txt | 4 +- host/lib/usrp/usrp_e100/fpga-downloader.cc | 274 ------------------------ host/lib/usrp/usrp_e100/fpga_downloader.cpp | 262 +++++++++++++++++++++++ host/usrp_e_utils/CMakeLists.txt | 6 +- host/usrp_e_utils/clkgen-config.cpp | 305 --------------------------- host/usrp_e_utils/clkgen_config.hpp | 310 ++++++++++++++++++++++++++++ host/usrp_e_utils/fpga-downloader.cpp | 267 ------------------------ host/usrp_e_utils/usrp-e-utility.cpp | 72 +++++++ 9 files changed, 657 insertions(+), 852 deletions(-) delete mode 100644 host/lib/usrp/usrp_e100/fpga-downloader.cc create mode 100644 host/lib/usrp/usrp_e100/fpga_downloader.cpp delete mode 100644 host/usrp_e_utils/clkgen-config.cpp create mode 100644 host/usrp_e_utils/clkgen_config.hpp delete mode 100644 host/usrp_e_utils/fpga-downloader.cpp create mode 100644 host/usrp_e_utils/usrp-e-utility.cpp (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/examples/rx_timed_samples.cpp b/host/examples/rx_timed_samples.cpp index 9ebe36c5a..630b4a7a9 100644 --- a/host/examples/rx_timed_samples.cpp +++ b/host/examples/rx_timed_samples.cpp @@ -32,7 +32,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::string args; double seconds_in_future; size_t total_num_samps; - double rate, freq; + double rate, freq, clock; //setup the program options po::options_description desc("Allowed options"); @@ -41,6 +41,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("args", po::value(&args)->default_value(""), "single uhd device address args") ("secs", po::value(&seconds_in_future)->default_value(3), "number of seconds in the future to receive") ("nsamps", po::value(&total_num_samps)->default_value(1000), "total number of samples to receive") + ("clock", po::value(&clock), "master clock frequency in Hz") ("rate", po::value(&rate)->default_value(100e6/16), "rate of incoming samples") ("freq", po::value(&freq)->default_value(0), "rf center frequency in Hz") ("dilv", "specify to disable inner-loop verbose") @@ -63,6 +64,12 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ uhd::usrp::multi_usrp::sptr usrp = uhd::usrp::multi_usrp::make(args); std::cout << boost::format("Using Device: %s") % usrp->get_pp_string() << std::endl; + //optionally set the clock rate (do before setting anything else) + if (vm.count("clock")){ + std::cout << boost::format("Setting master clock rate: %f MHz...") % (clock/1e6) << std::endl; + usrp->set_master_clock_rate(clock); + } + //set the rx sample rate std::cout << boost::format("Setting RX Rate: %f Msps...") % (rate/1e6) << std::endl; usrp->set_rx_rate(rate); diff --git a/host/lib/usrp/usrp_e100/CMakeLists.txt b/host/lib/usrp/usrp_e100/CMakeLists.txt index c32dd87f8..acbac177e 100644 --- a/host/lib/usrp/usrp_e100/CMakeLists.txt +++ b/host/lib/usrp/usrp_e100/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2010 Ettus Research LLC +# Copyright 2010-2011 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -40,7 +40,7 @@ IF(ENABLE_USRP_E100) ${CMAKE_CURRENT_SOURCE_DIR}/dboard_impl.cpp ${CMAKE_CURRENT_SOURCE_DIR}/dboard_iface.cpp ${CMAKE_CURRENT_SOURCE_DIR}/dsp_impl.cpp - ${CMAKE_CURRENT_SOURCE_DIR}/fpga-downloader.cc + ${CMAKE_CURRENT_SOURCE_DIR}/fpga_downloader.cpp ${CMAKE_CURRENT_SOURCE_DIR}/io_impl.cpp ${CMAKE_CURRENT_SOURCE_DIR}/mboard_impl.cpp ${CMAKE_CURRENT_SOURCE_DIR}/usrp_e100_impl.cpp diff --git a/host/lib/usrp/usrp_e100/fpga-downloader.cc b/host/lib/usrp/usrp_e100/fpga-downloader.cc deleted file mode 100644 index 4a3d3b9af..000000000 --- a/host/lib/usrp/usrp_e100/fpga-downloader.cc +++ /dev/null @@ -1,274 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -/* - * Configuration connections - * - * CCK - MCSPI1_CLK - * DIN - MCSPI1_MOSI - * PROG_B - GPIO_175 - output (change mux) - * DONE - GPIO_173 - input (change mux) - * INIT_B - GPIO_114 - input (change mux) - * -*/ - -const unsigned int PROG_B = 175; -const unsigned int DONE = 173; -const unsigned int INIT_B = 114; - -//static std::string bit_file = "safe_u1e.bin"; - -const int BUF_SIZE = 4096; - -enum gpio_direction {IN, OUT}; - -class gpio { - public: - - gpio(unsigned int gpio_num, gpio_direction pin_direction); - - bool get_value(); - void set_value(bool state); - - private: - - std::stringstream base_path; - std::fstream value_file; -}; - -class spidev { - public: - - spidev(std::string dev_name); - ~spidev(); - - void send(char *wbuf, char *rbuf, unsigned int nbytes); - - private: - - int fd; - -}; - -gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) -{ - std::fstream export_file; - - export_file.open("/sys/class/gpio/export", std::ios::out); - if (not export_file.is_open()) throw std::runtime_error( - "Failed to open gpio export file." - ); - - export_file << gpio_num << std::endl; - - base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; - - std::fstream direction_file; - std::string direction_file_name; - - if (gpio_num != 114) { - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; - } - - std::string value_file_name; - - value_file_name = base_path.str() + "/value"; - - value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); - if (!value_file.is_open()) - std::cout << "Failed to open value file." << std::endl; -} - -bool gpio::get_value() -{ - - std::string val; - - std::getline(value_file, val); - value_file.seekg(0); - - if (val == "0") - return false; - else if (val == "1") - return true; - else - std::cout << "Data read from value file|" << val << "|" << std::endl; - - return false; -} - -void gpio::set_value(bool state) -{ - - if (state) - value_file << "1" << std::endl; - else - value_file << "0" << std::endl; -} - -static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init) -{ - - prog.set_value(true); - prog.set_value(false); - prog.set_value(true); - -#if 0 - bool ready_to_program(false); - unsigned int count(0); - do { - ready_to_program = init.get_value(); - count++; - - sleep(1); - } while (count < 10 && !ready_to_program); - - if (count == 10) { - std::cout << "FPGA not ready for programming." << std::endl; - exit(-1); - } -#endif -} - -spidev::spidev(std::string fname) -{ - int ret; - int mode = 0; - int speed = 12000000; - int bits = 8; - - fd = open(fname.c_str(), O_RDWR); - - ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); - ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); - ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); -} - - -spidev::~spidev() -{ - close(fd); -} - -void spidev::send(char *buf, char *rbuf, unsigned int nbytes) -{ - int ret; - - struct spi_ioc_transfer tr; - tr.tx_buf = (unsigned long) buf; - tr.rx_buf = (unsigned long) rbuf; - tr.len = nbytes; - tr.delay_usecs = 0; - tr.speed_hz = 48000000; - tr.bits_per_word = 8; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - -} - -static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done) -{ - std::ifstream bitstream; - - std::cout << "File name - " << file_name.c_str() << std::endl; - - bitstream.open(file_name.c_str(), std::ios::binary); - if (!bitstream.is_open()) - std::cout << "File " << file_name << " not opened succesfully." << std::endl; - - spidev spi("/dev/spidev1.0"); - char buf[BUF_SIZE]; - char rbuf[BUF_SIZE]; - - do { - bitstream.read(buf, BUF_SIZE); - spi.send(buf, rbuf, bitstream.gcount()); - - if (error.get_value()) - std::cout << "INIT_B went high, error occured." << std::endl; - - if (!done.get_value()) - std::cout << "Configuration complete." << std::endl; - - } while (bitstream.gcount() == BUF_SIZE); -} - -/* -int main(int argc, char *argv[]) -{ - - gpio gpio_prog_b(PROG_B, OUT); - gpio gpio_init_b(INIT_B, IN); - gpio gpio_done (DONE, IN); - - if (argc == 2) - bit_file = argv[1]; - - std::cout << "FPGA config file: " << bit_file << std::endl; - - prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - - std::cout << "Done = " << gpio_done.get_value() << std::endl; - - send_file_to_fpga(bit_file, gpio_init_b, gpio_done); -} -*/ - -void usrp_e100_load_fpga(const std::string &bin_file){ - gpio gpio_prog_b(PROG_B, OUT); - gpio gpio_init_b(INIT_B, IN); - gpio gpio_done (DONE, IN); - - std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush; - - UHD_ASSERT_THROW(std::system("/sbin/rmmod usrp_e") == 0); - - prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - - std::cout << "done = " << gpio_done.get_value() << std::endl; - - send_file_to_fpga(bin_file, gpio_init_b, gpio_done); - - UHD_ASSERT_THROW(std::system("/sbin/modprobe usrp_e") == 0); - -} - diff --git a/host/lib/usrp/usrp_e100/fpga_downloader.cpp b/host/lib/usrp/usrp_e100/fpga_downloader.cpp new file mode 100644 index 000000000..926e6fcaf --- /dev/null +++ b/host/lib/usrp/usrp_e100/fpga_downloader.cpp @@ -0,0 +1,262 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* + * Configuration connections + * + * CCK - MCSPI1_CLK + * DIN - MCSPI1_MOSI + * PROG_B - GPIO_175 - output (change mux) + * DONE - GPIO_173 - input (change mux) + * INIT_B - GPIO_114 - input (change mux) + * +*/ + +namespace usrp_e_fpga_downloader_utility{ + +const unsigned int PROG_B = 175; +const unsigned int DONE = 173; +const unsigned int INIT_B = 114; + +//static std::string bit_file = "safe_u1e.bin"; + +const int BUF_SIZE = 4096; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction); + + bool get_value(); + void set_value(bool state); + + private: + + std::stringstream base_path; + std::fstream value_file; +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) +{ + std::fstream export_file; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (not export_file.is_open()) throw std::runtime_error( + "Failed to open gpio export file." + ); + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::fstream direction_file; + std::string direction_file_name; + + if (gpio_num != 114) { + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + } + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init) +{ + + prog.set_value(true); + prog.set_value(false); + prog.set_value(true); + +#if 0 + bool ready_to_program(false); + unsigned int count(0); + do { + ready_to_program = init.get_value(); + count++; + + sleep(1); + } while (count < 10 && !ready_to_program); + + if (count == 10) { + std::cout << "FPGA not ready for programming." << std::endl; + exit(-1); + } +#endif +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 8; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 48000000; + tr.bits_per_word = 8; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done) +{ + std::ifstream bitstream; + + bitstream.open(file_name.c_str(), std::ios::binary); + if (!bitstream.is_open()) throw std::runtime_error( + "Coult not open the file: " + file_name + ); + + spidev spi("/dev/spidev1.0"); + char buf[BUF_SIZE]; + char rbuf[BUF_SIZE]; + + do { + bitstream.read(buf, BUF_SIZE); + spi.send(buf, rbuf, bitstream.gcount()); + + if (error.get_value()) + std::cout << "INIT_B went high, error occured." << std::endl; + + if (!done.get_value()) + std::cout << "Configuration complete." << std::endl; + + } while (bitstream.gcount() == BUF_SIZE); +} + +}//namespace usrp_e_fpga_downloader_utility + +void usrp_e100_load_fpga(const std::string &bin_file){ + using namespace usrp_e_fpga_downloader_utility; + + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush; + + if(std::system("/sbin/rmmod usrp_e") != 0){ + std::cerr << "USRP-E100 FPGA downloader: could not unload usrp_e module" << std::endl; + } + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bin_file, gpio_init_b, gpio_done); + + if(std::system("/sbin/modprobe usrp_e") != 0){ + std::cerr << "USRP-E100 FPGA downloader: could not load usrp_e module" << std::endl; + } + +} + diff --git a/host/usrp_e_utils/CMakeLists.txt b/host/usrp_e_utils/CMakeLists.txt index 96842a684..5123af592 100644 --- a/host/usrp_e_utils/CMakeLists.txt +++ b/host/usrp_e_utils/CMakeLists.txt @@ -26,13 +26,13 @@ LIBUHD_REGISTER_COMPONENT("USRP-E Utils" ENABLE_USRP_E_UTILS OFF "LINUX_TARGET" IF(ENABLE_USRP_E_UTILS) ENABLE_LANGUAGE(C) + INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR}) INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100) INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include) INCLUDE_DIRECTORIES(${CMAKE_BINARY_DIR}/lib/ic_reg_maps) SET(usrp_e_utils_sources - fpga-downloader.cpp - clkgen-config.cpp + usrp-e-utility.cpp usrp-e-loopback.c usrp-e-wb-test.cpp usrp-e-debug-pins.c @@ -44,7 +44,7 @@ IF(ENABLE_USRP_E_UTILS) FOREACH(util_source ${usrp_e_utils_sources}) GET_FILENAME_COMPONENT(util_name ${util_source} NAME_WE) ADD_EXECUTABLE(${util_name} ${util_source}) - TARGET_LINK_LIBRARIES(${util_name} -lpthread) + TARGET_LINK_LIBRARIES(${util_name} ${Boost_LIBRARIES}) INSTALL(TARGETS ${util_name} RUNTIME DESTINATION ${PKG_DATA_DIR}/usrp_e_utils) ENDFOREACH(util_source) diff --git a/host/usrp_e_utils/clkgen-config.cpp b/host/usrp_e_utils/clkgen-config.cpp deleted file mode 100644 index 8d29efff1..000000000 --- a/host/usrp_e_utils/clkgen-config.cpp +++ /dev/null @@ -1,305 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. - * - * This file is part of UHD - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. -*/ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include "ad9522_regs.hpp" - -#include - - -const unsigned int CLKGEN_SELECT = 145; - -enum gpio_direction {IN, OUT}; - -class gpio { - public: - - gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action); - ~gpio(); - - bool get_value(); - void set_value(bool state); - - private: - - unsigned int gpio_num; - - std::stringstream base_path; - std::fstream value_file; - std::fstream direction_file; - bool close_action; // True set to input and release, false do nothing -}; - -class spidev { - public: - - spidev(std::string dev_name); - ~spidev(); - - void send(char *wbuf, char *rbuf, unsigned int nbytes); - - private: - - int fd; - -}; - -gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action) -{ - std::fstream export_file; - - gpio_num = _gpio_num; - - export_file.open("/sys/class/gpio/export", std::ios::out); - if (!export_file.is_open()) ///\todo Poor error handling - std::cout << "Failed to open gpio export file." << std::endl; - - export_file << gpio_num << std::endl; - - base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; - - std::string direction_file_name; - - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; - - std::string value_file_name; - - value_file_name = base_path.str() + "/value"; - - value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); - if (!value_file.is_open()) - std::cout << "Failed to open value file." << std::endl; -} - -bool gpio::get_value() -{ - - std::string val; - - std::getline(value_file, val); - value_file.seekg(0); - - if (val == "0") - return false; - else if (val == "1") - return true; - else - std::cout << "Data read from value file|" << val << "|" << std::endl; - - return false; -} - -void gpio::set_value(bool state) -{ - - if (state) - value_file << "1" << std::endl; - else - value_file << "0" << std::endl; -} - -gpio::~gpio() -{ - if (close_action) { - std::fstream unexport_file; - - direction_file << "in" << std::endl; - - unexport_file.open("/sys/class/gpio/unexport", std::ios::out); - if (!unexport_file.is_open()) ///\todo Poor error handling - std::cout << "Failed to open gpio export file." << std::endl; - - unexport_file << gpio_num << std::endl; - - } - -} - -spidev::spidev(std::string fname) -{ - int ret; - int mode = 0; - int speed = 12000; - int bits = 24; - - fd = open(fname.c_str(), O_RDWR); - - ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); - ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); - ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); -} - - -spidev::~spidev() -{ - close(fd); -} - -void spidev::send(char *buf, char *rbuf, unsigned int nbytes) -{ - int ret; - - struct spi_ioc_transfer tr; - tr.tx_buf = (unsigned long) buf; - tr.rx_buf = (unsigned long) rbuf; - tr.len = nbytes; - tr.delay_usecs = 0; - tr.speed_hz = 12000000; - tr.bits_per_word = 24; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - -} - -static void spi_write_word(spidev spi, gpio &chip_select, const unsigned int addr, const unsigned char data) { - unsigned char out_data[3], in_data[3]; - unsigned char rw_w1_w0 = 0; //write one byte - out_data[0] = (rw_w1_w0 << 5) | (addr >> 8); - out_data[1] = addr & 0xff; - out_data[2] = data; - - chip_select.set_value(0); - spi.send((char *)out_data, (char *)in_data, 4); - chip_select.set_value(1); -} - -static void send_config_to_clkgen(gpio &chip_select) -{ - spidev spi("/dev/spidev1.0"); - - //do a soft reset - spi_write_word(spi, chip_select, 0x000, 1 << 5 | 1 << 2); - spi_write_word(spi, chip_select, 0x232, 0x1); - - // init some registers; - ad9522_regs_t ad9522_regs; - ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; //use sdo and sdi - ad9522_regs.mirror = 1; //mirror sdo active - ad9522_regs.io_update = 1; //latch the registers - ad9522_regs.status_pin_control = 0x1; //n divider - ad9522_regs.ld_pin_control = 0x32; //show ref2 - ad9522_regs.refmon_pin_control = 0x12; //show ref2 - ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin as debug - - ad9522_regs.enable_ref2 = 0x1; - ad9522_regs.enable_ref1 = 0x0; - ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; - - ad9522_regs.set_r_counter(1); - ad9522_regs.a_counter = 0; - ad9522_regs.set_b_counter(20); - ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; - - ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; //normal mode - ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; - - ad9522_regs.vco_calibration_now = 1; //calibrate it! - ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; - ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; - - ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - ad9522_regs.divider0_low_cycles = 2; //3 low - ad9522_regs.divider0_high_cycles = 1; //2 high - ad9522_regs.divider1_low_cycles = 2; //3 low - ad9522_regs.divider1_high_cycles = 1; //2 high - - ad9522_regs.enable_eeprom_write = 1; - - //write the registers - int reg_list[] = {0, 4, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 240, 241, 242, 243, - 244, 245, 246, 247, 248, 249, 250, 251, 252, - 253, 400, 401, 402, 403, 404, 405, 406, 407, - 408, 409, 410, 411, 480, 481, 560, 562, 2818, - 2819}; - - for(int i=0; i<49; i++) { //blame std::vector for this (no static initialization bs) - spi_write_word(spi, chip_select, reg_list[i], ad9522_regs.get_reg(reg_list[i])); - } - - sleep(1); - - if (1){//write settings to eeprom - - //load the register buffs - spi_write_word(spi, chip_select, 0xa00, 0x0); - spi_write_word(spi, chip_select, 0xa01, 0x0); - spi_write_word(spi, chip_select, 0xa02, 0x0); - spi_write_word(spi, chip_select, 0xa03, 0x2); - spi_write_word(spi, chip_select, 0xa04, 0x0); - spi_write_word(spi, chip_select, 0xa05, 0x4); - spi_write_word(spi, chip_select, 0xa06, 0xe); - spi_write_word(spi, chip_select, 0xa07, 0x0); - spi_write_word(spi, chip_select, 0xa08, 0x10); - spi_write_word(spi, chip_select, 0xa09, 0xe); - spi_write_word(spi, chip_select, 0xa0a, 0x0); - spi_write_word(spi, chip_select, 0xa0b, 0xf0); - spi_write_word(spi, chip_select, 0xa0c, 0xb); - spi_write_word(spi, chip_select, 0xa0d, 0x1); - spi_write_word(spi, chip_select, 0xa0e, 0x90); - spi_write_word(spi, chip_select, 0xa0f, 0x1); - spi_write_word(spi, chip_select, 0xa10, 0x1); - spi_write_word(spi, chip_select, 0xa11, 0xe0); - spi_write_word(spi, chip_select, 0xa12, 0x1); - spi_write_word(spi, chip_select, 0xa13, 0x2); - spi_write_word(spi, chip_select, 0xa14, 0x30); - spi_write_word(spi, chip_select, 0xa15, 0x80); - spi_write_word(spi, chip_select, 0xa16, 0xff); - - spi_write_word(spi, chip_select, 0x232, 0x01); //latch - sleep(1); - //////////////////////////////////////////////////////////////// - - ad9522_regs.reg2eeprom = 1; - //write to eeprom - spi_write_word(spi, chip_select, 0xB03, ad9522_regs.get_reg(0xB03)); - //io update - spi_write_word(spi, chip_select, 0x232, ad9522_regs.get_reg(0x232)); //latch - sleep(1); - } - -} - -int main(int argc, char *argv[]) -{ - gpio clkgen_select(CLKGEN_SELECT, OUT, true); - - send_config_to_clkgen(clkgen_select); -} - diff --git a/host/usrp_e_utils/clkgen_config.hpp b/host/usrp_e_utils/clkgen_config.hpp new file mode 100644 index 000000000..0c9dc8de2 --- /dev/null +++ b/host/usrp_e_utils/clkgen_config.hpp @@ -0,0 +1,310 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef USRP_E_UTILS_CLKGEN_CONFIG_HPP +#define USRP_E_UTILS_CLKGEN_CONFIG_HPP + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "ad9522_regs.hpp" + +#include + +namespace usrp_e_clkgen_config_utility{ + +const unsigned int CLKGEN_SELECT = 145; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action); + ~gpio(); + + bool get_value(); + void set_value(bool state); + + private: + + unsigned int gpio_num; + + std::stringstream base_path; + std::fstream value_file; + std::fstream direction_file; + bool close_action; // True set to input and release, false do nothing +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action) +:close_action(close_action) +{ + std::fstream export_file; + + gpio_num = _gpio_num; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +gpio::~gpio() +{ + if (close_action) { + std::fstream unexport_file; + + direction_file << "in" << std::endl; + + unexport_file.open("/sys/class/gpio/unexport", std::ios::out); + if (!unexport_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + unexport_file << gpio_num << std::endl; + + } + +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000; + int bits = 24; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 12000000; + tr.bits_per_word = 24; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void spi_write_word(spidev spi, gpio &chip_select, const unsigned int addr, const unsigned char data) { + unsigned char out_data[3], in_data[3]; + unsigned char rw_w1_w0 = 0; //write one byte + out_data[0] = (rw_w1_w0 << 5) | (addr >> 8); + out_data[1] = addr & 0xff; + out_data[2] = data; + + chip_select.set_value(0); + spi.send((char *)out_data, (char *)in_data, 4); + chip_select.set_value(1); +} + +static void send_config_to_clkgen(gpio &chip_select) +{ + spidev spi("/dev/spidev1.0"); + + //do a soft reset + spi_write_word(spi, chip_select, 0x000, 1 << 5 | 1 << 2); + spi_write_word(spi, chip_select, 0x232, 0x1); + + // init some registers; + ad9522_regs_t ad9522_regs; + ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; //use sdo and sdi + ad9522_regs.mirror = 1; //mirror sdo active + ad9522_regs.io_update = 1; //latch the registers + ad9522_regs.status_pin_control = 0x1; //n divider + ad9522_regs.ld_pin_control = 0x32; //show ref2 + ad9522_regs.refmon_pin_control = 0x12; //show ref2 + ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin as debug + + ad9522_regs.enable_ref2 = 0x1; + ad9522_regs.enable_ref1 = 0x0; + ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + + ad9522_regs.set_r_counter(1); + ad9522_regs.a_counter = 0; + ad9522_regs.set_b_counter(20); + ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; + + ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; //normal mode + ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + + ad9522_regs.vco_calibration_now = 1; //calibrate it! + ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; + ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; + + ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + ad9522_regs.divider0_low_cycles = 2; //3 low + ad9522_regs.divider0_high_cycles = 1; //2 high + ad9522_regs.divider1_low_cycles = 2; //3 low + ad9522_regs.divider1_high_cycles = 1; //2 high + + ad9522_regs.enable_eeprom_write = 1; + + //write the registers + int reg_list[] = {0, 4, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 240, 241, 242, 243, + 244, 245, 246, 247, 248, 249, 250, 251, 252, + 253, 400, 401, 402, 403, 404, 405, 406, 407, + 408, 409, 410, 411, 480, 481, 560, 562, 2818, + 2819}; + + for(int i=0; i<49; i++) { //blame std::vector for this (no static initialization bs) + spi_write_word(spi, chip_select, reg_list[i], ad9522_regs.get_reg(reg_list[i])); + } + + sleep(1); + + if (1){//write settings to eeprom + + //load the register buffs + spi_write_word(spi, chip_select, 0xa00, 0x0); + spi_write_word(spi, chip_select, 0xa01, 0x0); + spi_write_word(spi, chip_select, 0xa02, 0x0); + spi_write_word(spi, chip_select, 0xa03, 0x2); + spi_write_word(spi, chip_select, 0xa04, 0x0); + spi_write_word(spi, chip_select, 0xa05, 0x4); + spi_write_word(spi, chip_select, 0xa06, 0xe); + spi_write_word(spi, chip_select, 0xa07, 0x0); + spi_write_word(spi, chip_select, 0xa08, 0x10); + spi_write_word(spi, chip_select, 0xa09, 0xe); + spi_write_word(spi, chip_select, 0xa0a, 0x0); + spi_write_word(spi, chip_select, 0xa0b, 0xf0); + spi_write_word(spi, chip_select, 0xa0c, 0xb); + spi_write_word(spi, chip_select, 0xa0d, 0x1); + spi_write_word(spi, chip_select, 0xa0e, 0x90); + spi_write_word(spi, chip_select, 0xa0f, 0x1); + spi_write_word(spi, chip_select, 0xa10, 0x1); + spi_write_word(spi, chip_select, 0xa11, 0xe0); + spi_write_word(spi, chip_select, 0xa12, 0x1); + spi_write_word(spi, chip_select, 0xa13, 0x2); + spi_write_word(spi, chip_select, 0xa14, 0x30); + spi_write_word(spi, chip_select, 0xa15, 0x80); + spi_write_word(spi, chip_select, 0xa16, 0xff); + + spi_write_word(spi, chip_select, 0x232, 0x01); //latch + sleep(1); + //////////////////////////////////////////////////////////////// + + ad9522_regs.reg2eeprom = 1; + //write to eeprom + spi_write_word(spi, chip_select, 0xB03, ad9522_regs.get_reg(0xB03)); + //io update + spi_write_word(spi, chip_select, 0x232, ad9522_regs.get_reg(0x232)); //latch + sleep(1); + } + +} + +}//namespace usrp_e_clkgen_config_utility + +//int main(int argc, char *argv[]) +static void clock_genconfig_main(void) +{ + using namespace usrp_e_clkgen_config_utility; + gpio clkgen_select(CLKGEN_SELECT, OUT, true); + + send_config_to_clkgen(clkgen_select); +} + +#endif /*USRP_E_UTILS_CLKGEN_CONFIG_HPP*/ diff --git a/host/usrp_e_utils/fpga-downloader.cpp b/host/usrp_e_utils/fpga-downloader.cpp deleted file mode 100644 index 80ee71600..000000000 --- a/host/usrp_e_utils/fpga-downloader.cpp +++ /dev/null @@ -1,267 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. -*/ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -/* - * Configuration connections - * - * CCK - MCSPI1_CLK - * DIN - MCSPI1_MOSI - * PROG_B - GPIO_175 - output (change mux) - * DONE - GPIO_173 - input (change mux) - * INIT_B - GPIO_114 - input (change mux) - * -*/ - -const unsigned int PROG_B = 175; -const unsigned int DONE = 173; -const unsigned int INIT_B = 114; - -static std::string bit_file = "safe_u1e.bin"; - -const int BUF_SIZE = 4096; - -enum gpio_direction {IN, OUT}; - -class gpio { - public: - - gpio(unsigned int gpio_num, gpio_direction pin_direction); - - bool get_value(); - void set_value(bool state); - - private: - - std::stringstream base_path; - std::fstream value_file; -}; - -class spidev { - public: - - spidev(std::string dev_name); - ~spidev(); - - void send(char *wbuf, char *rbuf, unsigned int nbytes); - - private: - - int fd; - -}; - -gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) -{ - std::fstream export_file; - - export_file.open("/sys/class/gpio/export", std::ios::out); - if (!export_file.is_open()) ///\todo Poor error handling - std::cout << "Failed to open gpio export file." << std::endl; - - export_file << gpio_num << std::endl; - - base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; - - std::fstream direction_file; - std::string direction_file_name; - - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; - - std::string value_file_name; - - value_file_name = base_path.str() + "/value"; - - value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); - if (!value_file.is_open()) - std::cout << "Failed to open value file." << std::endl; -} - -bool gpio::get_value() -{ - - std::string val; - - std::getline(value_file, val); - value_file.seekg(0); - - if (val == "0") - return false; - else if (val == "1") - return true; - else - std::cout << "Data read from value file|" << val << "|" << std::endl; - - return false; -} - -void gpio::set_value(bool state) -{ - - if (state) - value_file << "1" << std::endl; - else - value_file << "0" << std::endl; -} - -static void prepare_fpga_for_configuration(gpio &prog, gpio &init) -{ - - prog.set_value(true); - prog.set_value(false); - prog.set_value(true); - -#if 0 - bool ready_to_program(false); - unsigned int count(0); - do { - ready_to_program = init.get_value(); - count++; - - sleep(1); - } while (count < 10 && !ready_to_program); - - if (count == 10) { - std::cout << "FPGA not ready for programming." << std::endl; - exit(-1); - } -#endif -} - -spidev::spidev(std::string fname) -{ - int ret; - int mode = 0; - int speed = 12000000; - int bits = 8; - - fd = open(fname.c_str(), O_RDWR); - - ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); - ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); - ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); -} - - -spidev::~spidev() -{ - close(fd); -} - -void spidev::send(char *buf, char *rbuf, unsigned int nbytes) -{ - int ret; - - struct spi_ioc_transfer tr; - tr.tx_buf = (unsigned long) buf; - tr.rx_buf = (unsigned long) rbuf; - tr.len = nbytes; - tr.delay_usecs = 0; - tr.speed_hz = 48000000; - tr.bits_per_word = 8; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - -} - -static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done) -{ - std::ifstream bitstream; - - std::cout << "File name - " << file_name.c_str() << std::endl; - - bitstream.open(file_name.c_str(), std::ios::binary); - if (!bitstream.is_open()) - std::cout << "File " << file_name << " not opened succesfully." << std::endl; - - spidev spi("/dev/spidev1.0"); - char buf[BUF_SIZE]; - char rbuf[BUF_SIZE]; - - do { - bitstream.read(buf, BUF_SIZE); - spi.send(buf, rbuf, bitstream.gcount()); - - if (error.get_value()) - std::cout << "INIT_B went high, error occured." << std::endl; - - if (!done.get_value()) - std::cout << "Configuration complete." << std::endl; - - } while (bitstream.gcount() == BUF_SIZE); -} - -int main(int argc, char *argv[]) -{ - - gpio gpio_prog_b(PROG_B, OUT); - gpio gpio_init_b(INIT_B, IN); - gpio gpio_done (DONE, IN); - - if (argc == 2) - bit_file = argv[1]; - - bool module_found(false); - std::ifstream mod_file("/proc/modules"); - while (!mod_file.eof()) { - std::string line; - getline(mod_file, line); - if (line.find("usrp_e") != std::string::npos) - module_found = true; - } - mod_file.close(); - - if (module_found) { - std::cout << "USRP Embedded kernel module loaded, not loading FPGA." << std::endl; - return -1; - } - - std::cout << "FPGA config file: " << bit_file << std::endl; - - prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - - std::cout << "Done = " << gpio_done.get_value() << std::endl; - - send_file_to_fpga(bit_file, gpio_init_b, gpio_done); -} - diff --git a/host/usrp_e_utils/usrp-e-utility.cpp b/host/usrp_e_utils/usrp-e-utility.cpp new file mode 100644 index 000000000..139aabc30 --- /dev/null +++ b/host/usrp_e_utils/usrp-e-utility.cpp @@ -0,0 +1,72 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include + +#include "fpga_downloader.cpp" +#include "clkgen_config.hpp" + +namespace po = boost::program_options; + +static const std::string default_passthrough_path = "/usr/share/uhd/images/usrp_e1xx_passthrough.bin"; + +int UHD_SAFE_MAIN(int argc, char *argv[]){ + + //variables to be set by po + std::string fpga_path; + + //setup the program options + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("fpga", po::value(&fpga_path)->default_value(""), "loads the specified FPGA file") + ("reclk", "runs the clock recovery") + ; + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help")){ + std::cout << boost::format("UHD USRP-E Utility %s") % desc << std::endl; + return ~0; + } + + bool loaded_fpga_image = false; + if (vm.count("fpga")){ + std::cout << "USRP-E Utility loading the FPGA..." << std::endl << std::endl; + usrp_e100_load_fpga(fpga_path); + loaded_fpga_image = true; + sleep(1); + } + + if (vm.count("reclk")){ + std::cout << "USRP-E Utility running the clock recovery..." << std::endl << std::endl; + //if an image was not loaded or specified, we load pass-through + if (fpga_path.empty()) fpga_path = default_passthrough_path; + if (not loaded_fpga_image) usrp_e100_load_fpga(fpga_path); + clock_genconfig_main(); + std::system("rm /tmp/usrp*hash"); //clear hash so driver must reload + } + + std::cout << "Done!" << std::endl; + + return 0; +} -- cgit v1.2.3 From d27817a7ade49e74d29bf20a8ffa3ee35cbfe7ea Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 22 Jan 2011 14:02:53 +0000 Subject: usrp-e100: changes for global reset and non-zero sids on rx --- host/lib/usrp/usrp_e100/io_impl.cpp | 23 +++++++++++++++++------ host/lib/usrp/usrp_e100/usrp_e100_iface.cpp | 6 +++++- host/lib/usrp/usrp_e100/usrp_e100_impl.hpp | 2 +- host/lib/usrp/usrp_e100/usrp_e100_regs.hpp | 12 ++++++++++-- 4 files changed, 33 insertions(+), 10 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/usrp_e100/io_impl.cpp index 2388482c7..58faeafb0 100644 --- a/host/lib/usrp/usrp_e100/io_impl.cpp +++ b/host/lib/usrp/usrp_e100/io_impl.cpp @@ -35,7 +35,8 @@ zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface); /*********************************************************************** * Constants **********************************************************************/ -static const size_t tx_async_report_sid = 1; +static const size_t rx_data_inline_sid = 1; +static const size_t tx_async_report_sid = 2; static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; static const bool recv_debug = false; @@ -110,8 +111,17 @@ void usrp_e100_impl::io_impl::recv_pirate_loop(usrp_e100_clock_ctrl::sptr clock_ const boost::uint32_t *vrt_hdr = buff->cast(); vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); + //handle an rx data packet or inline message + if (if_packet_info.sid == rx_data_inline_sid){ + if (recv_debug) std::cout << "this is rx_data_inline_sid\n"; + //same number of frames as the data transport -> always immediate + recv_pirate_booty->push_with_wait(buff); + continue; + } + //handle a tx async report message if (if_packet_info.sid == tx_async_report_sid and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + if (recv_debug) std::cout << "this is tx_async_report_sid\n"; //fill in the async metadata async_metadata_t metadata; @@ -128,8 +138,7 @@ void usrp_e100_impl::io_impl::recv_pirate_loop(usrp_e100_clock_ctrl::sptr clock_ continue; } - //same number of frames as the data transport -> always immediate - recv_pirate_booty->push_with_wait(buff); + if (recv_debug) std::cout << "this is unknown packet\n"; }catch(const std::exception &e){ std::cerr << "Error (usrp-e recv pirate loop): " << e.what() << std::endl; @@ -153,17 +162,20 @@ void usrp_e100_impl::io_init(void){ //setup before the registers (transport called to calculate max spp) _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface)); + //clear state machines + _iface->poke32(UE_REG_CTRL_RX_CLEAR, 0); + _iface->poke32(UE_REG_CTRL_TX_CLEAR, 0); + //setup rx data path _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); - _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer | (0x3 << 22) //integer time other | (0x1 << 20) //fractional time sample count ); - _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, 0); + _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, rx_data_inline_sid); _iface->poke32(UE_REG_CTRL_RX_VRT_TRAILER, 0); //setup the tx policy @@ -185,7 +197,6 @@ void usrp_e100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ void usrp_e100_impl::handle_overrun(size_t){ std::cerr << "O"; //the famous OOOOOOOOOOO - _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 0); if (_io_impl->continuous_streaming){ this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); } diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp index 40c7afabb..ad36dd97a 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010 Ettus Research LLC +// Copyright 2010-2011 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -16,6 +16,7 @@ // #include "usrp_e100_iface.hpp" +#include "usrp_e100_regs.hpp" #include #include //ioctl #include //open, close @@ -108,6 +109,9 @@ public: throw std::runtime_error("Failed to open " + node); } + //very first thing, reset all the wishbone, always do first! + this->poke32(UE_REG_CLEAR_GLOBAL, 0); + mb_eeprom = mboard_eeprom_t(get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100); } diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp index df8e5dc9f..864e82099 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp @@ -30,7 +30,7 @@ #ifndef INCLUDED_USRP_E100_IMPL_HPP #define INCLUDED_USRP_E100_IMPL_HPP -static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; //make this 3 then the mainline fpga image gets fixed for embedded +static const boost::uint16_t USRP_E_COMPAT_NUM = 0x03; //! load an fpga image from a bin file into the usrp-e fpga extern void usrp_e100_load_fpga(const std::string &bin_file); diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp index 7dc3a4ba8..a030462d0 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp @@ -125,6 +125,14 @@ #define UE_REG_SR_MISC_TEST32 UE_REG_SETTINGS_BASE_ADDR(52) +///////////////////////////////////////////////// +// Magic reset regs +//////////////////////////////////////////////// +#define UE_REG_CLEAR_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(48) + (4*(n))) +#define UE_REG_CLEAR_RX UE_REG_CLEAR_ADDR(0) +#define UE_REG_CLEAR_TX UE_REG_CLEAR_ADDR(1) +#define UE_REG_CLEAR_GLOBAL UE_REG_CLEAR_ADDR(2) + ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// @@ -145,7 +153,7 @@ #define UE_REG_CTRL_RX_STREAM_CMD UE_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) #define UE_REG_CTRL_RX_TIME_SECS UE_REG_CTRL_RX_ADDR(1) #define UE_REG_CTRL_RX_TIME_TICKS UE_REG_CTRL_RX_ADDR(2) -#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_CTRL_RX_ADDR(3) // write anything to clear overrun +#define UE_REG_CTRL_RX_CLEAR UE_REG_CTRL_RX_ADDR(3) // write anything to clear #define UE_REG_CTRL_RX_VRT_HEADER UE_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter #define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_CTRL_RX_ADDR(5) // word 1 of packet. #define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_CTRL_RX_ADDR(6) @@ -167,7 +175,7 @@ //////////////////////////////////////////////// #define UE_REG_CTRL_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) #define UE_REG_CTRL_TX_NCHANNELS UE_REG_CTRL_TX_ADDR(0) -#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_CTRL_TX_ADDR(1) +#define UE_REG_CTRL_TX_CLEAR UE_REG_CTRL_TX_ADDR(1) #define UE_REG_CTRL_TX_REPORT_SID UE_REG_CTRL_TX_ADDR(2) #define UE_REG_CTRL_TX_POLICY UE_REG_CTRL_TX_ADDR(3) -- cgit v1.2.3 From 5b4d90582d827d7ba2483d7916b2f0400a5bd9fa Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 3 Feb 2011 11:20:37 -0800 Subject: usrp-e100: added passthrough to images makefile, tweaks to usrp-e-utility --- host/lib/usrp/usrp_e100/fpga_downloader.cpp | 2 +- host/usrp_e_utils/usrp-e-utility.cpp | 21 ++++++++++++--------- images/Makefile | 16 ++++++++++++++++ 3 files changed, 29 insertions(+), 10 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/fpga_downloader.cpp b/host/lib/usrp/usrp_e100/fpga_downloader.cpp index 926e6fcaf..c0013fcbd 100644 --- a/host/lib/usrp/usrp_e100/fpga_downloader.cpp +++ b/host/lib/usrp/usrp_e100/fpga_downloader.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010 Ettus Research LLC +// Copyright 2010-2011 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by diff --git a/host/usrp_e_utils/usrp-e-utility.cpp b/host/usrp_e_utils/usrp-e-utility.cpp index 139aabc30..4b4fc0178 100644 --- a/host/usrp_e_utils/usrp-e-utility.cpp +++ b/host/usrp_e_utils/usrp-e-utility.cpp @@ -18,6 +18,7 @@ #include #include #include +#include #include #include "fpga_downloader.cpp" @@ -25,8 +26,6 @@ namespace po = boost::program_options; -static const std::string default_passthrough_path = "/usr/share/uhd/images/usrp_e1xx_passthrough.bin"; - int UHD_SAFE_MAIN(int argc, char *argv[]){ //variables to be set by po @@ -36,8 +35,8 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ po::options_description desc("Allowed options"); desc.add_options() ("help", "help message") - ("fpga", po::value(&fpga_path)->default_value(""), "loads the specified FPGA file") - ("reclk", "runs the clock recovery") + ("fpga", po::value(&fpga_path), "loads the specified FPGA file") + ("reclk", "runs the clock recovery") ; po::variables_map vm; po::store(po::parse_command_line(argc, argv, desc), vm); @@ -50,20 +49,24 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ } bool loaded_fpga_image = false; - if (vm.count("fpga")){ + if (vm.count("fpga") != 0){ std::cout << "USRP-E Utility loading the FPGA..." << std::endl << std::endl; usrp_e100_load_fpga(fpga_path); loaded_fpga_image = true; sleep(1); } - if (vm.count("reclk")){ + if (vm.count("reclk") != 0){ std::cout << "USRP-E Utility running the clock recovery..." << std::endl << std::endl; //if an image was not loaded or specified, we load pass-through - if (fpga_path.empty()) fpga_path = default_passthrough_path; - if (not loaded_fpga_image) usrp_e100_load_fpga(fpga_path); + if (fpga_path.empty()) throw std::runtime_error( + "Please specify the path to the pass-though FPGA image for your device.\n" + " usrp-e-utility --reclk --fpga=/usr/share/uhd/images/usrp_e1xx_pt_fpga.bin" + ); clock_genconfig_main(); - std::system("rm /tmp/usrp*hash"); //clear hash so driver must reload + if (std::system("rm /tmp/usrp*hash") != 0){ //clear hash so driver must reload + std::cerr << "No hash to remove! Don't worry, its not a problem." << std::endl; + } } std::cout << "Done!" << std::endl; diff --git a/images/Makefile b/images/Makefile index 34c18cdc2..cfc783ee4 100644 --- a/images/Makefile +++ b/images/Makefile @@ -151,6 +151,22 @@ $(_usrp_e100_fpga_bin): $(GLOBAL_DEPS) endif +######################################################################## +# USRP-E100 pass-through fpga +######################################################################## +ifdef HAS_XTCLSH + +_usrp_e100_pt_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u1e_passthru +_usrp_e100_pt_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e100_pt_fpga.bin +IMAGES_LIST += $(_usrp_e100_pt_fpga_bin) + +$(_usrp_e100_pt_fpga_bin): $(GLOBAL_DEPS) + cd $(_usrp_e100_pt_fpga_dir) && make clean + cd $(_usrp_e100_pt_fpga_dir) && make bin + cp $(_usrp_e100_pt_fpga_dir)/build/passthru.bin $@ + +endif + ######################################################################## # Build rules ######################################################################## -- cgit v1.2.3 From 38185eb6f18e77245d358860872336d9998e1c07 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 27 Jan 2011 13:56:41 +0000 Subject: usrp-e100: tweak for clock control register calculation, works better --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 63 ++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 30 deletions(-) (limited to 'host/lib/usrp/usrp_e100') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 36ab1a8be..e29fe18ce 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -116,43 +116,46 @@ static clock_settings_type get_clock_settings(double rate){ const size_t X = i*ref_rate/gcd; const size_t Y = i*out_rate/gcd; - //determine chan_div, vco_div, and r_div - //and fill in that order of preference - cs.chan_divider = greatest_divisor(X, 32); - cs.vco_divider = greatest_divisor(X/cs.chan_divider, 6); - cs.r_counter = X/cs.chan_divider/cs.vco_divider; - - //avoid a vco divider of 1 (if possible) - if (cs.vco_divider == 1){ - cs.vco_divider = least_divisor(cs.chan_divider, 2); - cs.chan_divider /= cs.vco_divider; - } - //determine A and B (P is fixed) cs.b_counter = Y/cs.prescaler; cs.a_counter = Y - cs.b_counter*cs.prescaler; - if (CLOCK_SETTINGS_DEBUG){ - std::cout << "X " << X << std::endl; - std::cout << "Y " << Y << std::endl; - std::cout << cs.to_pp_string() << std::endl; - } + static const double vco_bound_pad = 100e6; + for ( //calculate an r divider that fits into the bounds of the vco + cs.r_counter = size_t(cs.get_n_counter()*cs.get_ref_rate()/(1800e6 - vco_bound_pad)); + cs.r_counter <= size_t(cs.get_n_counter()*cs.get_ref_rate()/(1400e6 + vco_bound_pad)) + and cs.r_counter > 0; cs.r_counter++ + ){ + + //determine chan_div and vco_div + //and fill in that order of preference + cs.chan_divider = greatest_divisor(X/cs.r_counter, 32); + cs.vco_divider = greatest_divisor(X/cs.chan_divider/cs.r_counter, 6); + + //avoid a vco divider of 1 (if possible) + if (cs.vco_divider == 1){ + cs.vco_divider = least_divisor(cs.chan_divider, 2); + cs.chan_divider /= cs.vco_divider; + } - //filter limits on the counters - if (cs.vco_divider == 1) continue; - if (cs.r_counter >= (1<<14)) continue; - if (cs.b_counter == 2) continue; - if (cs.b_counter == 1 and cs.a_counter != 0) continue; - if (cs.b_counter >= (1<<13)) continue; - if (cs.a_counter >= (1<<6)) continue; + if (CLOCK_SETTINGS_DEBUG){ + std::cout << "gcd " << gcd << std::endl; + std::cout << "X " << X << std::endl; + std::cout << "Y " << Y << std::endl; + std::cout << cs.to_pp_string() << std::endl; + } - //check the bounds on the vco - static const double vco_bound_pad = 100e6; - if (cs.get_vco_rate() > (1800e6 - vco_bound_pad)) continue; - if (cs.get_vco_rate() < (1400e6 + vco_bound_pad)) continue; + //filter limits on the counters + if (cs.vco_divider == 1) continue; + if (cs.r_counter >= (1<<14)) continue; + if (cs.b_counter == 2) continue; + if (cs.b_counter == 1 and cs.a_counter != 0) continue; + if (cs.b_counter >= (1<<13)) continue; + if (cs.a_counter >= (1<<6)) continue; - std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; - return cs; + std::cout << "USRP-E100 clock control: " << i << std::endl << cs.to_pp_string() << std::endl; + return cs; + } } throw std::runtime_error(str(boost::format( -- cgit v1.2.3