From f393d6fd8d0c1bef33a3f7346867d6a7e103df19 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 29 Jan 2011 16:11:21 +0000 Subject: usrp-e100: so far internal vco code works w/ 64mhz --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 195 ++++++++++++++++++++++----------- 1 file changed, 133 insertions(+), 62 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 4048218f2..5fd0466d8 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010 Ettus Research LLC +// Copyright 2010-2011 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -18,17 +18,27 @@ #include "clock_ctrl.hpp" #include "ad9522_regs.hpp" #include -#include #include #include "usrp_e100_regs.hpp" //spi slave constants #include #include #include +#include +#include #include #include using namespace uhd; +/*********************************************************************** + * Constants + **********************************************************************/ +static const bool ENABLE_THE_TEST_CLOCK_OUT = true; +static const double REFERENCE_INPUT_RATE = 10e6; + +/*********************************************************************** + * Helpers + **********************************************************************/ template static void set_clock_divider( size_t divider, div_type &low, div_type &high, bypass_type &bypass ){ @@ -41,13 +51,13 @@ template static void set_clock_divider * Clock rate calculation stuff: * Using the internal VCO between 1400 and 1800 MHz **********************************************************************/ -struct clock_settings_type{ - size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, clk_divider; +struct clock_settings_type : boost::totally_ordered{ + size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider; size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} - double get_ref_rate(void) const{return 10e6 * ref_clock_doubler;} + double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;} double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();} - double get_clk_rate(void) const{return get_vco_rate()/vco_divider;} - double get_out_rate(void) const{return get_clk_rate()/clk_divider;} + double get_chan_rate(void) const{return get_vco_rate()/vco_divider;} + double get_out_rate(void) const{return get_chan_rate()/chan_divider;} std::string to_pp_string(void) const{ return str(boost::format( " r_counter: %d\n" @@ -55,9 +65,9 @@ struct clock_settings_type{ " b_counter: %d\n" " prescaler: %d\n" " vco_divider: %d\n" - " clk_divider: %d\n" + " chan_divider: %d\n" " vco_rate: %fMHz\n" - " clk_rate: %fMHz\n" + " chan_rate: %fMHz\n" " out_rate: %fMHz\n" ) % r_counter @@ -65,53 +75,53 @@ struct clock_settings_type{ % b_counter % prescaler % vco_divider - % clk_divider + % chan_divider % (get_vco_rate()/1e6) - % (get_clk_rate()/1e6) + % (get_chan_rate()/1e6) % (get_out_rate()/1e6) ); } }; -UHD_SINGLETON_FCN(std::vector, get_clock_settings); +bool operator<(const clock_settings_type &lhs, const clock_settings_type &rhs){ + if (lhs.get_out_rate() != rhs.get_out_rate()) //sort small to large out rates + return lhs.get_out_rate() < rhs.get_out_rate(); + + if (lhs.r_counter != rhs.r_counter) //sort small to large r dividers + return lhs.r_counter < rhs.r_counter; + + if (lhs.get_vco_rate() != rhs.get_vco_rate()) //sort large to small vco rates + return lhs.get_vco_rate() > rhs.get_vco_rate(); + + return false; //whatever case +} + +static std::vector _get_clock_settings(void){ + std::vector clock_settings; -UHD_STATIC_BLOCK(libuhd_usrp_e100_reg_clock_rates){ clock_settings_type cs; cs.ref_clock_doubler = 2; //always doubling cs.prescaler = 8; //set to 8 when input is under 2400 MHz - for (cs.r_counter = 1; cs.r_counter <= 1; cs.r_counter++){ + for (cs.r_counter = 1; cs.r_counter <= 3; cs.r_counter++){ for (cs.b_counter = 3; cs.b_counter <= 10; cs.b_counter++){ for (cs.a_counter = 0; cs.a_counter <= 10; cs.a_counter++){ for (cs.vco_divider = 2; cs.vco_divider <= 6; cs.vco_divider++){ - for (cs.clk_divider = 1; cs.clk_divider <= 32; cs.clk_divider++){ + for (cs.chan_divider = 1; cs.chan_divider <= 32; cs.chan_divider++){ if (cs.get_vco_rate() > 1800e6) continue; if (cs.get_vco_rate() < 1400e6) continue; if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface - //std::cout << (cs.get_out_rate()/1e6) << std::endl; - get_clock_settings().push_back(cs); + clock_settings.push_back(cs); }}}}} -} - -/*********************************************************************** - * Constants - **********************************************************************/ -static const bool enable_test_clock = false; -static const size_t ref_clock_doubler = 2; //enabled below -static const double ref_clock_rate = 10e6 * ref_clock_doubler; - -static const size_t r_counter = 1; -static const size_t a_counter = 0; -static const size_t b_counter = 20 / ref_clock_doubler; -static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz -static const size_t vco_divider = 5; //set below with enum -static const size_t n_counter = prescaler * b_counter + a_counter; -static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz -static const double master_clock_rate = vco_clock_rate/vco_divider; + std::sort(clock_settings.begin(), clock_settings.end()); + return clock_settings; +} -static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); -static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); +static std::vector &get_clock_settings(void){ + static std::vector clock_settings = _get_clock_settings(); + return clock_settings; +} /*********************************************************************** * Clock Control Implementation @@ -120,6 +130,8 @@ class usrp_e100_clock_ctrl_impl : public usrp_e100_clock_ctrl{ public: usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface){ _iface = iface; + _chan_rate = 0.0; + _out_rate = 0.0; //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work @@ -134,16 +146,27 @@ public: this->set_fpga_clock_rate(64e6); //initialize to something + this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } ~usrp_e100_clock_ctrl_impl(void){ + this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } + /*********************************************************************** + * Clock rate control: + * - set clock rate w/ internal VCO + * - set clock rate w/ external VCXO + **********************************************************************/ void set_clock_settings_with_internal_vco(const clock_settings_type &cs){ + //set the rates to private variables so the implementation knows! + _chan_rate = cs.get_chan_rate(); + _out_rate = cs.get_out_rate(); + _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0; _ad9522_regs.set_r_counter(cs.r_counter); @@ -156,6 +179,7 @@ public: _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.vco_calibration_now = 1; //calibrate it! + _ad9522_regs.bypass_vco_divider = 0; switch(cs.vco_divider){ case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break; @@ -168,7 +192,7 @@ public: //setup fpga master clock _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - set_clock_divider(cs.clk_divider, + set_clock_divider(cs.chan_divider, _ad9522_regs.divider0_low_cycles, _ad9522_regs.divider0_high_cycles, _ad9522_regs.divider0_bypass @@ -176,44 +200,58 @@ public: //setup codec clock _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - set_clock_divider(cs.clk_divider, + set_clock_divider(cs.chan_divider, _ad9522_regs.divider1_low_cycles, _ad9522_regs.divider1_high_cycles, _ad9522_regs.divider1_bypass ); - //setup test clock (same divider as codec clock) - _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; - _ad9522_regs.out4_cmos_configuration = (enable_test_clock)? - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + this->send_all_regs(); + } - //setup a list of register ranges to write - typedef std::pair range_t; - static const std::vector ranges = boost::assign::list_of - (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) - (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) - (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) - ; + void set_clock_settings_with_external_vcxo(double rate){ + //set the rates to private variables so the implementation knows! + _chan_rate = rate; + _out_rate = rate; - //write initial register values and latch/update - BOOST_FOREACH(const range_t &range, ranges){ - for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ - this->send_reg(addr); - } - } - this->latch_regs(); + _ad9522_regs.enable_clock_doubler = 1; + + //bypass prescalers and counters == 1 + _ad9522_regs.set_r_counter(1); + _ad9522_regs.a_counter = 0; + _ad9522_regs.set_b_counter(1); + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; + + //setup external vcxo + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_ASYNC; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + _ad9522_regs.bypass_vco_divider = 1; + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + _ad9522_regs.divider0_bypass = 1; + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + _ad9522_regs.divider1_bypass = 1; + + this->send_all_regs(); } void set_fpga_clock_rate(double rate){ + if (_out_rate == rate) return; + if (rate == 61.44e6){ - //TODO special settings for external VCXO + set_clock_settings_with_external_vcxo(rate); } else{ BOOST_FOREACH(const clock_settings_type &cs, get_clock_settings()){ + //std::cout << cs.to_pp_string() << std::endl; if (rate != cs.get_out_rate()) continue; std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; set_clock_settings_with_internal_vco(cs); + return; //done here, exits loop } throw std::runtime_error(str(boost::format( "USRP-E100 clock control: could not find settings for clock rate %fMHz" @@ -222,7 +260,20 @@ public: } double get_fpga_clock_rate(void){ - return master_clock_rate/fpga_clock_divider; + return this->_out_rate; + } + + /*********************************************************************** + * Special test clock output + **********************************************************************/ + void enable_test_clock(bool enb){ + //setup test clock (same divider as codec clock) + _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; + _ad9522_regs.out4_cmos_configuration = (enb)? + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F0); + this->latch_regs(); } /*********************************************************************** @@ -240,13 +291,13 @@ public: std::vector get_rx_dboard_clock_rates(void){ std::vector rates; for(size_t div = 1; div <= 16+16; div++) - rates.push_back(master_clock_rate/div); + rates.push_back(this->_chan_rate/div); return rates; } void set_rx_dboard_clock_rate(double rate){ assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); - size_t divider = size_t(master_clock_rate/rate); + size_t divider = size_t(this->_chan_rate/rate); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider3_low_cycles, @@ -276,7 +327,7 @@ public: void set_tx_dboard_clock_rate(double rate){ assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); - size_t divider = size_t(master_clock_rate/rate); + size_t divider = size_t(this->_chan_rate/rate); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider2_low_cycles, @@ -317,6 +368,8 @@ public: private: usrp_e100_iface::sptr _iface; ad9522_regs_t _ad9522_regs; + double _out_rate; //rate at the fpga and codec + double _chan_rate; //rate before final dividers void latch_regs(void){ _ad9522_regs.io_update = 1; @@ -332,6 +385,24 @@ private: reg, 24, false /*no rb*/ ); } + + void send_all_regs(void){ + //setup a list of register ranges to write + typedef std::pair range_t; + static const std::vector ranges = boost::assign::list_of + (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) + (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) + (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) + ; + + //write initial register values and latch/update + BOOST_FOREACH(const range_t &range, ranges){ + for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ + this->send_reg(addr); + } + } + this->latch_regs(); + } }; /*********************************************************************** -- cgit v1.2.3 From ef6331f622aacadf233369637e08bfb7f2e6995a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 29 Jan 2011 20:29:12 +0000 Subject: usrp-e100: working clock control 61.44, 52mhz --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 5fd0466d8..e2c4889bc 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -33,8 +33,9 @@ using namespace uhd; /*********************************************************************** * Constants **********************************************************************/ -static const bool ENABLE_THE_TEST_CLOCK_OUT = true; +static const bool ENABLE_THE_TEST_OUT = false; static const double REFERENCE_INPUT_RATE = 10e6; +static const double DEFAULT_OUTPUT_RATE = 64e6; /*********************************************************************** * Helpers @@ -138,21 +139,22 @@ public: _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin - _ad9522_regs.status_pin_control = 0x1; //n divider + _ad9522_regs.status_pin_control = 0x2; //r divider _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 + _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_255CYC; this->use_internal_ref(); - this->set_fpga_clock_rate(64e6); //initialize to something + this->set_fpga_clock_rate(DEFAULT_OUTPUT_RATE); //initialize to something - this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); + this->enable_test_clock(ENABLE_THE_TEST_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } ~usrp_e100_clock_ctrl_impl(void){ - this->enable_test_clock(ENABLE_THE_TEST_CLOCK_OUT); + this->enable_test_clock(ENABLE_THE_TEST_OUT); this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } @@ -217,13 +219,13 @@ public: _ad9522_regs.enable_clock_doubler = 1; //bypass prescalers and counters == 1 - _ad9522_regs.set_r_counter(1); + _ad9522_regs.set_r_counter(125); _ad9522_regs.a_counter = 0; - _ad9522_regs.set_b_counter(1); + _ad9522_regs.set_b_counter(384); _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; //setup external vcxo - _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_ASYNC; + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.bypass_vco_divider = 1; _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_EXTERNAL; -- cgit v1.2.3 From 572a64f0acb459583abfccbc8288158822fa2f77 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 29 Jan 2011 21:03:29 +0000 Subject: usrp-e100: clock control use boost math gcd for divider calculation --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index e2c4889bc..dd7f8507b 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -24,6 +24,7 @@ #include #include #include +#include //gcd #include #include #include @@ -216,12 +217,14 @@ public: _chan_rate = rate; _out_rate = rate; - _ad9522_regs.enable_clock_doubler = 1; + _ad9522_regs.enable_clock_doubler = 1; //doubler always on + const double ref_rate = REFERENCE_INPUT_RATE*2; - //bypass prescalers and counters == 1 - _ad9522_regs.set_r_counter(125); + //bypass prescaler such that N = B + long gcd = boost::math::gcd(long(ref_rate), long(rate)); + _ad9522_regs.set_r_counter(int(ref_rate/gcd)); _ad9522_regs.a_counter = 0; - _ad9522_regs.set_b_counter(384); + _ad9522_regs.set_b_counter(int(rate/gcd)); _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV1; //setup external vcxo -- cgit v1.2.3 From 8aea3fb21dda08bcb64ff00a07de448615818a98 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 30 Jan 2011 20:39:26 -0800 Subject: usrp-e100: work on clock control --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 123 +++++++++++++++++++++++++++------ host/lib/usrp/usrp_e100/clock_ctrl.hpp | 7 ++ 2 files changed, 108 insertions(+), 22 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 1fb1a7125..4048218f2 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -18,10 +18,12 @@ #include "clock_ctrl.hpp" #include "ad9522_regs.hpp" #include +#include #include #include "usrp_e100_regs.hpp" //spi slave constants #include #include +#include #include #include @@ -35,6 +37,62 @@ template static void set_clock_divider bypass = (divider == 1)? 1 : 0; } +/*********************************************************************** + * Clock rate calculation stuff: + * Using the internal VCO between 1400 and 1800 MHz + **********************************************************************/ +struct clock_settings_type{ + size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, clk_divider; + size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} + double get_ref_rate(void) const{return 10e6 * ref_clock_doubler;} + double get_vco_rate(void) const{return get_ref_rate()/r_counter * get_n_counter();} + double get_clk_rate(void) const{return get_vco_rate()/vco_divider;} + double get_out_rate(void) const{return get_clk_rate()/clk_divider;} + std::string to_pp_string(void) const{ + return str(boost::format( + " r_counter: %d\n" + " a_counter: %d\n" + " b_counter: %d\n" + " prescaler: %d\n" + " vco_divider: %d\n" + " clk_divider: %d\n" + " vco_rate: %fMHz\n" + " clk_rate: %fMHz\n" + " out_rate: %fMHz\n" + ) + % r_counter + % a_counter + % b_counter + % prescaler + % vco_divider + % clk_divider + % (get_vco_rate()/1e6) + % (get_clk_rate()/1e6) + % (get_out_rate()/1e6) + ); + } +}; + +UHD_SINGLETON_FCN(std::vector, get_clock_settings); + +UHD_STATIC_BLOCK(libuhd_usrp_e100_reg_clock_rates){ + clock_settings_type cs; + cs.ref_clock_doubler = 2; //always doubling + cs.prescaler = 8; //set to 8 when input is under 2400 MHz + + for (cs.r_counter = 1; cs.r_counter <= 1; cs.r_counter++){ + for (cs.b_counter = 3; cs.b_counter <= 10; cs.b_counter++){ + for (cs.a_counter = 0; cs.a_counter <= 10; cs.a_counter++){ + for (cs.vco_divider = 2; cs.vco_divider <= 6; cs.vco_divider++){ + for (cs.clk_divider = 1; cs.clk_divider <= 32; cs.clk_divider++){ + if (cs.get_vco_rate() > 1800e6) continue; + if (cs.get_vco_rate() < 1400e6) continue; + if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface + //std::cout << (cs.get_out_rate()/1e6) << std::endl; + get_clock_settings().push_back(cs); + }}}}} +} + /*********************************************************************** * Constants **********************************************************************/ @@ -72,25 +130,45 @@ public: _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 - _ad9522_regs.enable_ref2 = 1; - _ad9522_regs.enable_ref1 = 0; - _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + this->use_internal_ref(); - _ad9522_regs.set_r_counter(r_counter); - _ad9522_regs.a_counter = a_counter; - _ad9522_regs.set_b_counter(b_counter); + this->set_fpga_clock_rate(64e6); //initialize to something + + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + ~usrp_e100_clock_ctrl_impl(void){ + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + void set_clock_settings_with_internal_vco(const clock_settings_type &cs){ + _ad9522_regs.enable_clock_doubler = (cs.ref_clock_doubler == 2)? 1 : 0; + + _ad9522_regs.set_r_counter(cs.r_counter); + _ad9522_regs.a_counter = cs.a_counter; + _ad9522_regs.set_b_counter(cs.b_counter); + UHD_ASSERT_THROW(cs.prescaler == 8); //assumes this below: _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.vco_calibration_now = 1; //calibrate it! - _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; + switch(cs.vco_divider){ + case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; + case 2: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV2; break; + case 3: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV3; break; + case 4: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV4; break; + case 5: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; break; + case 6: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV6; break; + } _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; //setup fpga master clock _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - set_clock_divider(fpga_clock_divider, + set_clock_divider(cs.clk_divider, _ad9522_regs.divider0_low_cycles, _ad9522_regs.divider0_high_cycles, _ad9522_regs.divider0_bypass @@ -98,7 +176,7 @@ public: //setup codec clock _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - set_clock_divider(codec_clock_divider, + set_clock_divider(cs.clk_divider, _ad9522_regs.divider1_low_cycles, _ad9522_regs.divider1_high_cycles, _ad9522_regs.divider1_bypass @@ -125,21 +203,22 @@ public: } } this->latch_regs(); - //test read: - //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b); - //boost::uint32_t result = _iface->transact_spi( - // UE_SPI_SS_AD9522, - // spi_config_t::EDGE_RISE, - // reg, 24, true /*no*/ - //); - //std::cout << "result " << std::hex << result << std::endl; - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); } - ~usrp_e100_clock_ctrl_impl(void){ - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); + void set_fpga_clock_rate(double rate){ + if (rate == 61.44e6){ + //TODO special settings for external VCXO + } + else{ + BOOST_FOREACH(const clock_settings_type &cs, get_clock_settings()){ + if (rate != cs.get_out_rate()) continue; + std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; + set_clock_settings_with_internal_vco(cs); + } + throw std::runtime_error(str(boost::format( + "USRP-E100 clock control: could not find settings for clock rate %fMHz" + ) % (rate/1e6))); + } } double get_fpga_clock_rate(void){ diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp index d613d1473..1f9960ce4 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp @@ -39,6 +39,13 @@ public: */ static sptr make(usrp_e100_iface::sptr iface); + /*! + * Set the rate of the fpga clock line. + * Throws if rate is not valid. + * \param rate the new rate in Hz + */ + virtual void set_fpga_clock_rate(double rate) = 0; + /*! * Get the rate of the fpga clock line. * \return the fpga clock rate in Hz -- cgit v1.2.3 From cd45fb6be615a6f133e2c62a46f7c5eba76f72c1 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 31 Jan 2011 09:59:44 -0800 Subject: usrp-e100: remove unused clock control constants, enb test clock --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 4048218f2..a8d88fa42 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -96,22 +96,7 @@ UHD_STATIC_BLOCK(libuhd_usrp_e100_reg_clock_rates){ /*********************************************************************** * Constants **********************************************************************/ -static const bool enable_test_clock = false; -static const size_t ref_clock_doubler = 2; //enabled below -static const double ref_clock_rate = 10e6 * ref_clock_doubler; - -static const size_t r_counter = 1; -static const size_t a_counter = 0; -static const size_t b_counter = 20 / ref_clock_doubler; -static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz -static const size_t vco_divider = 5; //set below with enum - -static const size_t n_counter = prescaler * b_counter + a_counter; -static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz -static const double master_clock_rate = vco_clock_rate/vco_divider; - -static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); -static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); +static const bool enable_test_clock = true; /*********************************************************************** * Clock Control Implementation -- cgit v1.2.3 From 4afdcd180e5ee6b93fefe2fb07b071452fb7ef3f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 30 Jan 2011 15:04:15 +0000 Subject: usrp-e100: tweaks to clock control and setting from api --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 12 +++++++----- host/lib/usrp/usrp_e100/mboard_impl.cpp | 8 ++++++++ 2 files changed, 15 insertions(+), 5 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 05a27c38b..ef5e9b5ec 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -115,12 +115,15 @@ static std::vector _get_clock_settings(void){ if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface clock_settings.push_back(cs); }}}}} + + std::sort(clock_settings.begin(), clock_settings.end()); + return clock_settings; } -/*********************************************************************** - * Constants - **********************************************************************/ -static const bool enable_test_clock = true; +static std::vector &get_clock_settings(void){ + static std::vector clock_settings = _get_clock_settings(); + return clock_settings; +} /*********************************************************************** * Clock Control Implementation @@ -135,7 +138,6 @@ public: //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; - _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin _ad9522_regs.status_pin_control = 0x2; //r divider _ad9522_regs.ld_pin_control = 0x00; //dld diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index f52d2e6fb..0e08cd435 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -152,6 +152,10 @@ void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; } + case MBOARD_PROP_CLOCK_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -211,6 +215,10 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){ update_clock_config(); return; + case MBOARD_PROP_CLOCK_RATE: + _clock_ctrl->set_fpga_clock_rate(val.as()); + return; + default: UHD_THROW_PROP_SET_ERROR(); } } -- cgit v1.2.3 From 7b03f4144a0dc7a1e745ac43a3997b0eab7042c0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 30 Jan 2011 22:10:49 +0000 Subject: usrp-e100: work on clock control added vco calibration routine and readback to check for calibrated changed the counters/dividers calculation to be event driven and more mathematically calculated. --- host/lib/ic_reg_maps/gen_ad9522_regs.py | 8 ++ host/lib/usrp/usrp_e100/clock_ctrl.cpp | 151 +++++++++++++++++++++----------- 2 files changed, 106 insertions(+), 53 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py index a5debe568..86605c34a 100755 --- a/host/lib/ic_reg_maps/gen_ad9522_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py @@ -80,6 +80,14 @@ external_zero_delay_fcds 0x01E[4:3] 0 enable_external_zero_delay 0x01E[2] 0 enable_zero_delay 0x01E[1] 0 ######################################################################## +vco_calibration_finished 0x01F[6] 0 +holdover_active 0x01F[5] 0 +ref2_selected 0x01F[4] 0 +vco_freq_gt_thresh 0x01F[3] 0 +ref2_freq_gt_thresh 0x01F[2] 0 +ref1_freq_gt_thresh 0x01F[1] 0 +digital_lock_detect 0x01F[0] 0 +######################################################################## #for $i in range(12) #set $addr = ($i + 0x0F0) out$(i)_format $(addr)[7] 0 lvds, cmos diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index ef5e9b5ec..36ab1a8be 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include //gcd #include #include @@ -34,7 +34,8 @@ using namespace uhd; /*********************************************************************** * Constants **********************************************************************/ -static const bool ENABLE_THE_TEST_OUT = false; +static const bool CLOCK_SETTINGS_DEBUG = false; +static const bool ENABLE_THE_TEST_OUT = true; static const double REFERENCE_INPUT_RATE = 10e6; static const double DEFAULT_OUTPUT_RATE = 64e6; @@ -53,7 +54,7 @@ template static void set_clock_divider * Clock rate calculation stuff: * Using the internal VCO between 1400 and 1800 MHz **********************************************************************/ -struct clock_settings_type : boost::totally_ordered{ +struct clock_settings_type{ size_t ref_clock_doubler, r_counter, a_counter, b_counter, prescaler, vco_divider, chan_divider; size_t get_n_counter(void) const{return prescaler * b_counter + a_counter;} double get_ref_rate(void) const{return REFERENCE_INPUT_RATE * ref_clock_doubler;} @@ -85,44 +86,78 @@ struct clock_settings_type : boost::totally_ordered{ } }; -bool operator<(const clock_settings_type &lhs, const clock_settings_type &rhs){ - if (lhs.get_out_rate() != rhs.get_out_rate()) //sort small to large out rates - return lhs.get_out_rate() < rhs.get_out_rate(); - - if (lhs.r_counter != rhs.r_counter) //sort small to large r dividers - return lhs.r_counter < rhs.r_counter; - - if (lhs.get_vco_rate() != rhs.get_vco_rate()) //sort large to small vco rates - return lhs.get_vco_rate() > rhs.get_vco_rate(); - - return false; //whatever case +//! gives the greatest divisor of num between 1 and max inclusive +template static inline T greatest_divisor(T num, T max){ + for (T i = max; i > 1; i--) if (num%i == 0) return i; return 1; } -static std::vector _get_clock_settings(void){ - std::vector clock_settings; +//! gives the least divisor of num between min and num exclusive +template static inline T least_divisor(T num, T min){ + for (T i = min; i < num; i++) if (num%i == 0) return i; return 1; +} +static clock_settings_type get_clock_settings(double rate){ clock_settings_type cs; cs.ref_clock_doubler = 2; //always doubling cs.prescaler = 8; //set to 8 when input is under 2400 MHz - for (cs.r_counter = 1; cs.r_counter <= 3; cs.r_counter++){ - for (cs.b_counter = 3; cs.b_counter <= 10; cs.b_counter++){ - for (cs.a_counter = 0; cs.a_counter <= 10; cs.a_counter++){ - for (cs.vco_divider = 2; cs.vco_divider <= 6; cs.vco_divider++){ - for (cs.chan_divider = 1; cs.chan_divider <= 32; cs.chan_divider++){ - if (cs.get_vco_rate() > 1800e6) continue; - if (cs.get_vco_rate() < 1400e6) continue; - if (cs.get_out_rate() < 32e6) continue; //lowest we allow for GPMC interface - clock_settings.push_back(cs); - }}}}} - - std::sort(clock_settings.begin(), clock_settings.end()); - return clock_settings; -} + //basic formulas used below: + //out_rate*X = ref_rate*Y + //X = i*ref_rate/gcd + //Y = i*out_rate/gcd + //X = chan_div * vco_div * R + //Y = P*B + A + + const boost::uint64_t out_rate = boost::uint64_t(rate); + const boost::uint64_t ref_rate = boost::uint64_t(cs.get_ref_rate()); + const size_t gcd = size_t(boost::math::gcd(ref_rate, out_rate)); + + for (size_t i = 1; i <= 100; i++){ + const size_t X = i*ref_rate/gcd; + const size_t Y = i*out_rate/gcd; + + //determine chan_div, vco_div, and r_div + //and fill in that order of preference + cs.chan_divider = greatest_divisor(X, 32); + cs.vco_divider = greatest_divisor(X/cs.chan_divider, 6); + cs.r_counter = X/cs.chan_divider/cs.vco_divider; + + //avoid a vco divider of 1 (if possible) + if (cs.vco_divider == 1){ + cs.vco_divider = least_divisor(cs.chan_divider, 2); + cs.chan_divider /= cs.vco_divider; + } + + //determine A and B (P is fixed) + cs.b_counter = Y/cs.prescaler; + cs.a_counter = Y - cs.b_counter*cs.prescaler; + + if (CLOCK_SETTINGS_DEBUG){ + std::cout << "X " << X << std::endl; + std::cout << "Y " << Y << std::endl; + std::cout << cs.to_pp_string() << std::endl; + } + + //filter limits on the counters + if (cs.vco_divider == 1) continue; + if (cs.r_counter >= (1<<14)) continue; + if (cs.b_counter == 2) continue; + if (cs.b_counter == 1 and cs.a_counter != 0) continue; + if (cs.b_counter >= (1<<13)) continue; + if (cs.a_counter >= (1<<6)) continue; + + //check the bounds on the vco + static const double vco_bound_pad = 100e6; + if (cs.get_vco_rate() > (1800e6 - vco_bound_pad)) continue; + if (cs.get_vco_rate() < (1400e6 + vco_bound_pad)) continue; + + std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; + return cs; + } -static std::vector &get_clock_settings(void){ - static std::vector clock_settings = _get_clock_settings(); - return clock_settings; + throw std::runtime_error(str(boost::format( + "USRP-E100 clock control: could not calculate settings for clock rate %fMHz" + ) % (rate/1e6))); } /*********************************************************************** @@ -139,10 +174,10 @@ public: //Note: out0 should already be clocking the FPGA or this isnt going to work _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin - _ad9522_regs.status_pin_control = 0x2; //r divider + _ad9522_regs.status_pin_control = 0x1; //n divider _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 - _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_255CYC; + _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; this->use_internal_ref(); @@ -164,7 +199,9 @@ public: * - set clock rate w/ internal VCO * - set clock rate w/ external VCXO **********************************************************************/ - void set_clock_settings_with_internal_vco(const clock_settings_type &cs){ + void set_clock_settings_with_internal_vco(double rate){ + const clock_settings_type cs = get_clock_settings(rate); + //set the rates to private variables so the implementation knows! _chan_rate = cs.get_chan_rate(); _out_rate = cs.get_out_rate(); @@ -180,7 +217,6 @@ public: _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; - _ad9522_regs.vco_calibration_now = 1; //calibrate it! _ad9522_regs.bypass_vco_divider = 0; switch(cs.vco_divider){ case 1: _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; break; @@ -209,6 +245,7 @@ public: ); this->send_all_regs(); + calibrate_now(); } void set_clock_settings_with_external_vcxo(double rate){ @@ -245,22 +282,8 @@ public: void set_fpga_clock_rate(double rate){ if (_out_rate == rate) return; - - if (rate == 61.44e6){ - set_clock_settings_with_external_vcxo(rate); - } - else{ - BOOST_FOREACH(const clock_settings_type &cs, get_clock_settings()){ - //std::cout << cs.to_pp_string() << std::endl; - if (rate != cs.get_out_rate()) continue; - std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; - set_clock_settings_with_internal_vco(cs); - return; //done here, exits loop - } - throw std::runtime_error(str(boost::format( - "USRP-E100 clock control: could not find settings for clock rate %fMHz" - ) % (rate/1e6))); - } + if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate); + else set_clock_settings_with_internal_vco(rate); } double get_fpga_clock_rate(void){ @@ -390,6 +413,28 @@ private: ); } + void calibrate_now(void){ + //vco calibration routine: + _ad9522_regs.vco_calibration_now = 0; + this->send_reg(0x18); + this->latch_regs(); + _ad9522_regs.vco_calibration_now = 1; + this->send_reg(0x18); + this->latch_regs(); + //wait for calibration done: + static const boost::uint8_t addr = 0x01F; + for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::uint32_t reg = _iface->transact_spi( + UE_SPI_SS_AD9522, spi_config_t::EDGE_RISE, + _ad9522_regs.get_read_reg(addr), 24, true /*rb*/ + ); + _ad9522_regs.set_reg(addr, reg); + if (_ad9522_regs.vco_calibration_finished) return; + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + } + std::cerr << "USRP-E100 clock control: VCO calibration timeout" << std::endl; + } + void send_all_regs(void){ //setup a list of register ranges to write typedef std::pair range_t; -- cgit v1.2.3 From 38185eb6f18e77245d358860872336d9998e1c07 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 27 Jan 2011 13:56:41 +0000 Subject: usrp-e100: tweak for clock control register calculation, works better --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 63 ++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 30 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 36ab1a8be..e29fe18ce 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -116,43 +116,46 @@ static clock_settings_type get_clock_settings(double rate){ const size_t X = i*ref_rate/gcd; const size_t Y = i*out_rate/gcd; - //determine chan_div, vco_div, and r_div - //and fill in that order of preference - cs.chan_divider = greatest_divisor(X, 32); - cs.vco_divider = greatest_divisor(X/cs.chan_divider, 6); - cs.r_counter = X/cs.chan_divider/cs.vco_divider; - - //avoid a vco divider of 1 (if possible) - if (cs.vco_divider == 1){ - cs.vco_divider = least_divisor(cs.chan_divider, 2); - cs.chan_divider /= cs.vco_divider; - } - //determine A and B (P is fixed) cs.b_counter = Y/cs.prescaler; cs.a_counter = Y - cs.b_counter*cs.prescaler; - if (CLOCK_SETTINGS_DEBUG){ - std::cout << "X " << X << std::endl; - std::cout << "Y " << Y << std::endl; - std::cout << cs.to_pp_string() << std::endl; - } + static const double vco_bound_pad = 100e6; + for ( //calculate an r divider that fits into the bounds of the vco + cs.r_counter = size_t(cs.get_n_counter()*cs.get_ref_rate()/(1800e6 - vco_bound_pad)); + cs.r_counter <= size_t(cs.get_n_counter()*cs.get_ref_rate()/(1400e6 + vco_bound_pad)) + and cs.r_counter > 0; cs.r_counter++ + ){ + + //determine chan_div and vco_div + //and fill in that order of preference + cs.chan_divider = greatest_divisor(X/cs.r_counter, 32); + cs.vco_divider = greatest_divisor(X/cs.chan_divider/cs.r_counter, 6); + + //avoid a vco divider of 1 (if possible) + if (cs.vco_divider == 1){ + cs.vco_divider = least_divisor(cs.chan_divider, 2); + cs.chan_divider /= cs.vco_divider; + } - //filter limits on the counters - if (cs.vco_divider == 1) continue; - if (cs.r_counter >= (1<<14)) continue; - if (cs.b_counter == 2) continue; - if (cs.b_counter == 1 and cs.a_counter != 0) continue; - if (cs.b_counter >= (1<<13)) continue; - if (cs.a_counter >= (1<<6)) continue; + if (CLOCK_SETTINGS_DEBUG){ + std::cout << "gcd " << gcd << std::endl; + std::cout << "X " << X << std::endl; + std::cout << "Y " << Y << std::endl; + std::cout << cs.to_pp_string() << std::endl; + } - //check the bounds on the vco - static const double vco_bound_pad = 100e6; - if (cs.get_vco_rate() > (1800e6 - vco_bound_pad)) continue; - if (cs.get_vco_rate() < (1400e6 + vco_bound_pad)) continue; + //filter limits on the counters + if (cs.vco_divider == 1) continue; + if (cs.r_counter >= (1<<14)) continue; + if (cs.b_counter == 2) continue; + if (cs.b_counter == 1 and cs.a_counter != 0) continue; + if (cs.b_counter >= (1<<13)) continue; + if (cs.a_counter >= (1<<6)) continue; - std::cout << "USRP-E100 clock control:" << std::endl << cs.to_pp_string() << std::endl; - return cs; + std::cout << "USRP-E100 clock control: " << i << std::endl << cs.to_pp_string() << std::endl; + return cs; + } } throw std::runtime_error(str(boost::format( -- cgit v1.2.3