From ce5940f86e896b639e8fe60e2901a9d59f739785 Mon Sep 17 00:00:00 2001 From: Jason Abele Date: Mon, 26 Jul 2010 15:35:35 -0700 Subject: DBSRX support in UHD --- host/lib/usrp/usrp2/clock_ctrl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp/usrp2') diff --git a/host/lib/usrp/usrp2/clock_ctrl.cpp b/host/lib/usrp/usrp2/clock_ctrl.cpp index b9be037c0..02227afad 100644 --- a/host/lib/usrp/usrp2/clock_ctrl.cpp +++ b/host/lib/usrp/usrp2/clock_ctrl.cpp @@ -86,7 +86,7 @@ public: void set_rate_rx_dboard_clock(double rate){ assert_has(get_rates_rx_dboard_clock(), rate, "rx dboard clock rate"); - size_t divider = size_t(rate/get_master_clock_rate()); + size_t divider = size_t(get_master_clock_rate()/rate); //bypass when the divider ratio is one _ad9510_regs.bypass_divider_out7 = (divider == 1)? 1 : 0; //calculate the low and high dividers @@ -118,7 +118,7 @@ public: void set_rate_tx_dboard_clock(double rate){ assert_has(get_rates_tx_dboard_clock(), rate, "tx dboard clock rate"); - size_t divider = size_t(rate/get_master_clock_rate()); + size_t divider = size_t(get_master_clock_rate()/rate); //bypass when the divider ratio is one _ad9510_regs.bypass_divider_out6 = (divider == 1)? 1 : 0; //calculate the low and high dividers -- cgit v1.2.3