From b369d0f020f324b872099fcdbe321f5eac2f98bb Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Fri, 4 Jun 2010 17:35:48 -0700
Subject: usrp2 regs naming convention
---
host/lib/usrp/usrp2/codec_ctrl.cpp | 4 +-
host/lib/usrp/usrp2/dboard_iface.cpp | 28 ++++----
host/lib/usrp/usrp2/dboard_impl.cpp | 4 +-
host/lib/usrp/usrp2/dsp_impl.cpp | 12 ++--
host/lib/usrp/usrp2/io_impl.cpp | 12 ++--
host/lib/usrp/usrp2/mboard_impl.cpp | 32 ++++-----
host/lib/usrp/usrp2/serdes_ctrl.cpp | 4 +-
host/lib/usrp/usrp2/usrp2_regs.hpp | 132 +++++++++++++++++------------------
8 files changed, 114 insertions(+), 114 deletions(-)
(limited to 'host/lib/usrp/usrp2')
diff --git a/host/lib/usrp/usrp2/codec_ctrl.cpp b/host/lib/usrp/usrp2/codec_ctrl.cpp
index abd840027..32cc13ded 100644
--- a/host/lib/usrp/usrp2/codec_ctrl.cpp
+++ b/host/lib/usrp/usrp2/codec_ctrl.cpp
@@ -57,7 +57,7 @@ public:
}
//power-up adc
- _iface->poke32(FR_MISC_CTRL_ADC, FRF_MISC_CTRL_ADC_ON);
+ _iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_ON);
}
~usrp2_codec_ctrl_impl(void){
@@ -66,7 +66,7 @@ public:
this->send_ad9777_reg(0);
//power-down adc
- _iface->poke32(FR_MISC_CTRL_ADC, FRF_MISC_CTRL_ADC_OFF);
+ _iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_OFF);
}
private:
diff --git a/host/lib/usrp/usrp2/dboard_iface.cpp b/host/lib/usrp/usrp2/dboard_iface.cpp
index feee0a970..9f7c7f9e6 100644
--- a/host/lib/usrp/usrp2/dboard_iface.cpp
+++ b/host/lib/usrp/usrp2/dboard_iface.cpp
@@ -140,13 +140,13 @@ void usrp2_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){
boost::uint32_t new_sels = 0x0;
for(size_t i = 0; i < 16; i++){
bool is_bit_set = (value & (0x1 << i)) != 0;
- new_sels |= ((is_bit_set)? FRF_GPIO_SEL_ATR : FRF_GPIO_SEL_GPIO) << (i*2);
+ new_sels |= ((is_bit_set)? U2_FLAG_GPIO_SEL_ATR : U2_FLAG_GPIO_SEL_GPIO) << (i*2);
}
//write the selection mux value to register
switch(unit){
- case UNIT_RX: _iface->poke32(FR_GPIO_RX_SEL, new_sels); return;
- case UNIT_TX: _iface->poke32(FR_GPIO_TX_SEL, new_sels); return;
+ case UNIT_RX: _iface->poke32(U2_REG_GPIO_RX_SEL, new_sels); return;
+ case UNIT_TX: _iface->poke32(U2_REG_GPIO_TX_SEL, new_sels); return;
}
}
@@ -154,18 +154,18 @@ void usrp2_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){
_ddr_shadow = \
(_ddr_shadow & ~(0xffff << unit_to_shift[unit])) |
(boost::uint32_t(value) << unit_to_shift[unit]);
- _iface->poke32(FR_GPIO_DDR, _ddr_shadow);
+ _iface->poke32(U2_REG_GPIO_DDR, _ddr_shadow);
}
void usrp2_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){
_gpio_shadow = \
(_gpio_shadow & ~(0xffff << unit_to_shift[unit])) |
(boost::uint32_t(value) << unit_to_shift[unit]);
- _iface->poke32(FR_GPIO_IO, _gpio_shadow);
+ _iface->poke32(U2_REG_GPIO_IO, _gpio_shadow);
}
boost::uint16_t usrp2_dboard_iface::read_gpio(unit_t unit){
- return boost::uint16_t(_iface->peek32(FR_GPIO_IO) >> unit_to_shift[unit]);
+ return boost::uint16_t(_iface->peek32(U2_REG_GPIO_IO) >> unit_to_shift[unit]);
}
void usrp2_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){
@@ -174,16 +174,16 @@ void usrp2_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t
unit_t, uhd::dict<atr_reg_t, boost::uint32_t>
> unit_to_atr_to_addr = map_list_of
(UNIT_RX, map_list_of
- (ATR_REG_IDLE, FR_ATR_IDLE_RXSIDE)
- (ATR_REG_TX_ONLY, FR_ATR_INTX_RXSIDE)
- (ATR_REG_RX_ONLY, FR_ATR_INRX_RXSIDE)
- (ATR_REG_FULL_DUPLEX, FR_ATR_FULL_RXSIDE)
+ (ATR_REG_IDLE, U2_REG_ATR_IDLE_RXSIDE)
+ (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_RXSIDE)
+ (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_RXSIDE)
+ (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_RXSIDE)
)
(UNIT_TX, map_list_of
- (ATR_REG_IDLE, FR_ATR_IDLE_TXSIDE)
- (ATR_REG_TX_ONLY, FR_ATR_INTX_TXSIDE)
- (ATR_REG_RX_ONLY, FR_ATR_INRX_TXSIDE)
- (ATR_REG_FULL_DUPLEX, FR_ATR_FULL_TXSIDE)
+ (ATR_REG_IDLE, U2_REG_ATR_IDLE_TXSIDE)
+ (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_TXSIDE)
+ (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_TXSIDE)
+ (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_TXSIDE)
)
;
_iface->poke16(unit_to_atr_to_addr[unit][atr], value);
diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp
index 0ac39d2a3..4a3a70467 100644
--- a/host/lib/usrp/usrp2/dboard_impl.cpp
+++ b/host/lib/usrp/usrp2/dboard_impl.cpp
@@ -76,7 +76,7 @@ void usrp2_impl::update_rx_mux_config(void){
rx_mux = (((rx_mux >> 0) & 0x3) << 2) | (((rx_mux >> 2) & 0x3) << 0);
}
- _iface->poke32(FR_DSP_RX_MUX, rx_mux);
+ _iface->poke32(U2_REG_DSP_RX_MUX, rx_mux);
}
void usrp2_impl::update_tx_mux_config(void){
@@ -89,7 +89,7 @@ void usrp2_impl::update_tx_mux_config(void){
tx_mux = (((tx_mux >> 0) & 0xf) << 4) | (((tx_mux >> 4) & 0xf) << 0);
}
- _iface->poke32(FR_DSP_TX_MUX, tx_mux);
+ _iface->poke32(U2_REG_DSP_TX_MUX, tx_mux);
}
/***********************************************************************
diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp
index 195a9bc53..0d70811dd 100644
--- a/host/lib/usrp/usrp2/dsp_impl.cpp
+++ b/host/lib/usrp/usrp2/dsp_impl.cpp
@@ -98,11 +98,11 @@ void usrp2_impl::init_ddc_config(void){
void usrp2_impl::update_ddc_config(void){
//set the decimation
- _iface->poke32(FR_DSP_RX_DECIM_RATE, calculate_cic_word(_ddc_decim));
+ _iface->poke32(U2_REG_DSP_RX_DECIM_RATE, calculate_cic_word(_ddc_decim));
//set the scaling
static const boost::int16_t default_rx_scale_iq = 1024;
- _iface->poke32(FR_DSP_RX_SCALE_IQ,
+ _iface->poke32(U2_REG_DSP_RX_SCALE_IQ,
calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
);
}
@@ -141,7 +141,7 @@ void usrp2_impl::ddc_set(const wax::obj &key, const wax::obj &val){
case DSP_PROP_FREQ_SHIFT:{
double new_freq = val.as<double>();
- _iface->poke32(FR_DSP_RX_FREQ,
+ _iface->poke32(U2_REG_DSP_RX_FREQ,
calculate_freq_word_and_update_actual_freq(new_freq, get_master_clock_freq())
);
_ddc_freq = new_freq; //shadow
@@ -184,10 +184,10 @@ void usrp2_impl::update_duc_config(void){
boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed));
//set the interpolation
- _iface->poke32(FR_DSP_TX_INTERP_RATE, calculate_cic_word(_duc_interp));
+ _iface->poke32(U2_REG_DSP_TX_INTERP_RATE, calculate_cic_word(_duc_interp));
//set the scaling
- _iface->poke32(FR_DSP_TX_SCALE_IQ, calculate_iq_scale_word(scale, scale));
+ _iface->poke32(U2_REG_DSP_TX_SCALE_IQ, calculate_iq_scale_word(scale, scale));
}
/***********************************************************************
@@ -224,7 +224,7 @@ void usrp2_impl::duc_set(const wax::obj &key, const wax::obj &val){
case DSP_PROP_FREQ_SHIFT:{
double new_freq = val.as<double>();
- _iface->poke32(FR_DSP_TX_FREQ,
+ _iface->poke32(U2_REG_DSP_TX_FREQ,
calculate_freq_word_and_update_actual_freq(new_freq, get_master_clock_freq())
);
_duc_freq = new_freq; //shadow
diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp
index 18f2d013f..1c7113197 100644
--- a/host/lib/usrp/usrp2/io_impl.cpp
+++ b/host/lib/usrp/usrp2/io_impl.cpp
@@ -107,17 +107,17 @@ void usrp2_impl::io_init(void){
//setup RX DSP regs
std::cout << "RX samples per packet: " << get_max_recv_samps_per_packet() << std::endl;
- _iface->poke32(FR_RX_CTRL_NSAMPS_PER_PKT, get_max_recv_samps_per_packet());
- _iface->poke32(FR_RX_CTRL_NCHANNELS, 1);
- _iface->poke32(FR_RX_CTRL_CLEAR_OVERRUN, 1); //reset
- _iface->poke32(FR_RX_CTRL_VRT_HEADER, 0
+ _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, get_max_recv_samps_per_packet());
+ _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1);
+ _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset
+ _iface->poke32(U2_REG_RX_CTRL_VRT_HEADER, 0
| (0x1 << 28) //if data with stream id
| (0x1 << 26) //has trailer
| (0x3 << 22) //integer time other
| (0x1 << 20) //fractional time sample count
);
- _iface->poke32(FR_RX_CTRL_VRT_STREAM_ID, 0);
- _iface->poke32(FR_RX_CTRL_VRT_TRAILER, 0);
+ _iface->poke32(U2_REG_RX_CTRL_VRT_STREAM_ID, 0);
+ _iface->poke32(U2_REG_RX_CTRL_VRT_TRAILER, 0);
std::cout << "TX samples per packet: " << get_max_send_samps_per_packet() << std::endl;
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index a2aeadf16..78fc5dc23 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -54,26 +54,26 @@ void usrp2_impl::update_clock_config(void){
//translate pps source enums
switch(_clock_config.pps_source){
- case clock_config_t::PPS_SMA: pps_flags |= FRF_TIME64_PPS_SMA; break;
- case clock_config_t::PPS_MIMO: pps_flags |= FRF_TIME64_PPS_MIMO; break;
+ case clock_config_t::PPS_SMA: pps_flags |= U2_FLAG_TIME64_PPS_SMA; break;
+ case clock_config_t::PPS_MIMO: pps_flags |= U2_FLAG_TIME64_PPS_MIMO; break;
default: throw std::runtime_error("usrp2: unhandled clock configuration pps source");
}
//translate pps polarity enums
switch(_clock_config.pps_polarity){
- case clock_config_t::PPS_POS: pps_flags |= FRF_TIME64_PPS_POSEDGE; break;
- case clock_config_t::PPS_NEG: pps_flags |= FRF_TIME64_PPS_NEGEDGE; break;
+ case clock_config_t::PPS_POS: pps_flags |= U2_FLAG_TIME64_PPS_POSEDGE; break;
+ case clock_config_t::PPS_NEG: pps_flags |= U2_FLAG_TIME64_PPS_NEGEDGE; break;
default: throw std::runtime_error("usrp2: unhandled clock configuration pps polarity");
}
//set the pps flags
- _iface->poke32(FR_TIME64_FLAGS, pps_flags);
+ _iface->poke32(U2_REG_TIME64_FLAGS, pps_flags);
//clock source ref 10mhz
switch(_clock_config.ref_source){
- case clock_config_t::REF_INT : _iface->poke32(FR_MISC_CTRL_CLOCK, 0x10); break;
- case clock_config_t::REF_SMA : _iface->poke32(FR_MISC_CTRL_CLOCK, 0x1C); break;
- case clock_config_t::REF_MIMO: _iface->poke32(FR_MISC_CTRL_CLOCK, 0x15); break;
+ case clock_config_t::REF_INT : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x10); break;
+ case clock_config_t::REF_SMA : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x1C); break;
+ case clock_config_t::REF_MIMO: _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x15); break;
default: throw std::runtime_error("usrp2: unhandled clock configuration reference source");
}
@@ -84,18 +84,18 @@ void usrp2_impl::update_clock_config(void){
void usrp2_impl::set_time_spec(const time_spec_t &time_spec, bool now){
//set the ticks
- _iface->poke32(FR_TIME64_TICKS, time_spec.get_ticks(get_master_clock_freq()));
+ _iface->poke32(U2_REG_TIME64_TICKS, time_spec.get_ticks(get_master_clock_freq()));
//set the flags register
- boost::uint32_t imm_flags = (now)? FRF_TIME64_LATCH_NOW : FRF_TIME64_LATCH_NEXT_PPS;
- _iface->poke32(FR_TIME64_IMM, imm_flags);
+ boost::uint32_t imm_flags = (now)? U2_FLAG_TIME64_LATCH_NOW : U2_FLAG_TIME64_LATCH_NEXT_PPS;
+ _iface->poke32(U2_REG_TIME64_IMM, imm_flags);
//set the seconds (latches in all 3 registers)
- _iface->poke32(FR_TIME64_SECS, time_spec.secs);
+ _iface->poke32(U2_REG_TIME64_SECS, time_spec.secs);
}
void usrp2_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
- UHD_ASSERT_THROW(stream_cmd.num_samps <= FR_RX_CTRL_MAX_SAMPS_PER_CMD);
+ UHD_ASSERT_THROW(stream_cmd.num_samps <= U2_REG_RX_CTRL_MAX_SAMPS_PER_CMD);
//setup the mode to instruction flags
typedef boost::tuple<bool, bool, bool> inst_t;
@@ -112,14 +112,14 @@ void usrp2_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
boost::tie(inst_reload, inst_chain, inst_samps) = mode_to_inst[stream_cmd.stream_mode];
//issue the stream command
- _iface->poke32(FR_RX_CTRL_STREAM_CMD, FR_RX_CTRL_MAKE_CMD(
+ _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD, U2_REG_RX_CTRL_MAKE_CMD(
(inst_samps)? stream_cmd.num_samps : ((inst_chain)? get_max_recv_samps_per_packet() : 1),
(stream_cmd.stream_now)? 1 : 0,
(inst_chain)? 1 : 0,
(inst_reload)? 1 : 0
));
- _iface->poke32(FR_RX_CTRL_TIME_SECS, stream_cmd.time_spec.secs);
- _iface->poke32(FR_RX_CTRL_TIME_TICKS, stream_cmd.time_spec.get_ticks(get_master_clock_freq()));
+ _iface->poke32(U2_REG_RX_CTRL_TIME_SECS, stream_cmd.time_spec.secs);
+ _iface->poke32(U2_REG_RX_CTRL_TIME_TICKS, stream_cmd.time_spec.get_ticks(get_master_clock_freq()));
}
/***********************************************************************
diff --git a/host/lib/usrp/usrp2/serdes_ctrl.cpp b/host/lib/usrp/usrp2/serdes_ctrl.cpp
index 31708d377..e83dceb96 100644
--- a/host/lib/usrp/usrp2/serdes_ctrl.cpp
+++ b/host/lib/usrp/usrp2/serdes_ctrl.cpp
@@ -27,11 +27,11 @@ class usrp2_serdes_ctrl_impl : public usrp2_serdes_ctrl{
public:
usrp2_serdes_ctrl_impl(usrp2_iface::sptr iface){
_iface = iface;
- _iface->poke32(FR_MISC_CTRL_SERDES, FRF_MISC_CTRL_SERDES_ENABLE | FRF_MISC_CTRL_SERDES_RXEN);
+ _iface->poke32(U2_REG_MISC_CTRL_SERDES, U2_FLAG_MISC_CTRL_SERDES_ENABLE | U2_FLAG_MISC_CTRL_SERDES_RXEN);
}
~usrp2_serdes_ctrl_impl(void){
- _iface->poke32(FR_MISC_CTRL_SERDES, 0); //power-down
+ _iface->poke32(U2_REG_MISC_CTRL_SERDES, 0); //power-down
}
private:
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 0f675357b..589fa71a3 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -64,23 +64,23 @@
/////////////////////////////////////////////////
// Misc Control
////////////////////////////////////////////////
-#define FR_MISC_CTRL_CLOCK _SR_ADDR(0)
-#define FR_MISC_CTRL_SERDES _SR_ADDR(1)
-#define FR_MISC_CTRL_ADC _SR_ADDR(2)
-#define FR_MISC_CTRL_LEDS _SR_ADDR(3)
-#define FR_MISC_CTRL_PHY _SR_ADDR(4) // LSB is reset line to eth phy
-#define FR_MISC_CTRL_DBG_MUX _SR_ADDR(5)
-#define FR_MISC_CTRL_RAM_PAGE _SR_ADDR(6) // FIXME should go somewhere else...
-#define FR_MISC_CTRL_FLUSH_ICACHE _SR_ADDR(7) // Flush the icache
-#define FR_MISC_CTRL_LED_SRC _SR_ADDR(8) // HW or SW control for LEDs
-
-#define FRF_MISC_CTRL_SERDES_ENABLE 8
-#define FRF_MISC_CTRL_SERDES_PRBSEN 4
-#define FRF_MISC_CTRL_SERDES_LOOPEN 2
-#define FRF_MISC_CTRL_SERDES_RXEN 1
-
-#define FRF_MISC_CTRL_ADC_ON 0x0F
-#define FRF_MISC_CTRL_ADC_OFF 0x00
+#define U2_REG_MISC_CTRL_CLOCK _SR_ADDR(0)
+#define U2_REG_MISC_CTRL_SERDES _SR_ADDR(1)
+#define U2_REG_MISC_CTRL_ADC _SR_ADDR(2)
+#define U2_REG_MISC_CTRL_LEDS _SR_ADDR(3)
+#define U2_REG_MISC_CTRL_PHY _SR_ADDR(4) // LSB is reset line to eth phy
+#define U2_REG_MISC_CTRL_DBG_MUX _SR_ADDR(5)
+#define U2_REG_MISC_CTRL_RAM_PAGE _SR_ADDR(6) // FIXME should go somewhere else...
+#define U2_REG_MISC_CTRL_FLUSH_ICACHE _SR_ADDR(7) // Flush the icache
+#define U2_REG_MISC_CTRL_LED_SRC _SR_ADDR(8) // HW or SW control for LEDs
+
+#define U2_FLAG_MISC_CTRL_SERDES_ENABLE 8
+#define U2_FLAG_MISC_CTRL_SERDES_PRBSEN 4
+#define U2_FLAG_MISC_CTRL_SERDES_LOOPEN 2
+#define U2_FLAG_MISC_CTRL_SERDES_RXEN 1
+
+#define U2_FLAG_MISC_CTRL_ADC_ON 0x0F
+#define U2_FLAG_MISC_CTRL_ADC_OFF 0x00
/////////////////////////////////////////////////
// VITA49 64 bit time (write only)
@@ -101,26 +101,26 @@
*
* </pre>
*/
-#define FR_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS
-#define FR_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS
-#define FR_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above
-#define FR_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+#define U2_REG_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS
+#define U2_REG_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS
+#define U2_REG_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above
+#define U2_REG_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0)
//pps flags (see above)
-#define FRF_TIME64_PPS_NEGEDGE (0 << 0)
-#define FRF_TIME64_PPS_POSEDGE (1 << 0)
-#define FRF_TIME64_PPS_SMA (0 << 1)
-#define FRF_TIME64_PPS_MIMO (1 << 1)
+#define U2_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
+#define U2_FLAG_TIME64_PPS_POSEDGE (1 << 0)
+#define U2_FLAG_TIME64_PPS_SMA (0 << 1)
+#define U2_FLAG_TIME64_PPS_MIMO (1 << 1)
-#define FRF_TIME64_LATCH_NOW 1
-#define FRF_TIME64_LATCH_NEXT_PPS 0
+#define U2_FLAG_TIME64_LATCH_NOW 1
+#define U2_FLAG_TIME64_LATCH_NEXT_PPS 0
/////////////////////////////////////////////////
// DSP TX Regs
////////////////////////////////////////////////
-#define FR_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0)
-#define FR_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q}
-#define FR_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2)
+#define U2_REG_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0)
+#define U2_REG_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q}
+#define U2_REG_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2)
/*!
* \brief output mux configuration.
@@ -156,17 +156,17 @@
* The default value is 0x10
* </pre>
*/
-#define FR_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4)
+#define U2_REG_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4)
/////////////////////////////////////////////////
// DSP RX Regs
////////////////////////////////////////////////
-#define FR_DSP_RX_FREQ _SR_ADDR(SR_RX_DSP + 0)
-#define FR_DSP_RX_SCALE_IQ _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q}
-#define FR_DSP_RX_DECIM_RATE _SR_ADDR(SR_RX_DSP + 2)
-#define FR_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits,
+#define U2_REG_DSP_RX_FREQ _SR_ADDR(SR_RX_DSP + 0)
+#define U2_REG_DSP_RX_SCALE_IQ _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q}
+#define U2_REG_DSP_RX_DECIM_RATE _SR_ADDR(SR_RX_DSP + 2)
+#define U2_REG_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits,
// otherwise it is automatic
-#define FR_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits
+#define U2_REG_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits
/*!
* \brief input mux configuration.
*
@@ -188,7 +188,7 @@
* The default value is 0x4
* </pre>
*/
-#define FR_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v
+#define U2_REG_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v
////////////////////////////////////////////////
// GPIO, Slave 4
@@ -196,52 +196,52 @@
//
// These go to the daughterboard i/o pins
//
-#define FR_GPIO_BASE 0xC800
+#define U2_REG_GPIO_BASE 0xC800
-#define FR_GPIO_IO FR_GPIO_BASE + 0 // 32 bits, gpio io pins (tx high 16 bits, rx low 16 bits)
-#define FR_GPIO_DDR FR_GPIO_BASE + 4 // 32 bits, gpio ddr, 1 means output (tx high 16 bits, rx low 16 bits)
-#define FR_GPIO_TX_SEL FR_GPIO_BASE + 8 // 16 2-bit fields select which source goes to TX DB
-#define FR_GPIO_RX_SEL FR_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB
+#define U2_REG_GPIO_IO U2_REG_GPIO_BASE + 0 // 32 bits, gpio io pins (tx high 16 bits, rx low 16 bits)
+#define U2_REG_GPIO_DDR U2_REG_GPIO_BASE + 4 // 32 bits, gpio ddr, 1 means output (tx high 16 bits, rx low 16 bits)
+#define U2_REG_GPIO_TX_SEL U2_REG_GPIO_BASE + 8 // 16 2-bit fields select which source goes to TX DB
+#define U2_REG_GPIO_RX_SEL U2_REG_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB
// each 2-bit sel field is layed out this way
-#define FRF_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register
-#define FRF_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
-#define FRF_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric
-#define FRF_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric
+#define U2_FLAG_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register
+#define U2_FLAG_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
+#define U2_FLAG_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric
+#define U2_FLAG_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric
///////////////////////////////////////////////////
// ATR Controller, Slave 11
////////////////////////////////////////////////
-#define FR_ATR_BASE 0xE400
+#define U2_REG_ATR_BASE 0xE400
-#define FR_ATR_IDLE_TXSIDE FR_ATR_BASE + 0
-#define FR_ATR_IDLE_RXSIDE FR_ATR_BASE + 2
-#define FR_ATR_INTX_TXSIDE FR_ATR_BASE + 4
-#define FR_ATR_INTX_RXSIDE FR_ATR_BASE + 6
-#define FR_ATR_INRX_TXSIDE FR_ATR_BASE + 8
-#define FR_ATR_INRX_RXSIDE FR_ATR_BASE + 10
-#define FR_ATR_FULL_TXSIDE FR_ATR_BASE + 12
-#define FR_ATR_FULL_RXSIDE FR_ATR_BASE + 14
+#define U2_REG_ATR_IDLE_TXSIDE U2_REG_ATR_BASE + 0
+#define U2_REG_ATR_IDLE_RXSIDE U2_REG_ATR_BASE + 2
+#define U2_REG_ATR_INTX_TXSIDE U2_REG_ATR_BASE + 4
+#define U2_REG_ATR_INTX_RXSIDE U2_REG_ATR_BASE + 6
+#define U2_REG_ATR_INRX_TXSIDE U2_REG_ATR_BASE + 8
+#define U2_REG_ATR_INRX_RXSIDE U2_REG_ATR_BASE + 10
+#define U2_REG_ATR_FULL_TXSIDE U2_REG_ATR_BASE + 12
+#define U2_REG_ATR_FULL_RXSIDE U2_REG_ATR_BASE + 14
///////////////////////////////////////////////////
// VITA RX CTRL regs
///////////////////////////////////////////////////
// The following 3 are logically a single command register.
// They are clocked into the underlying fifo when time_ticks is written.
-#define FR_RX_CTRL_STREAM_CMD _SR_ADDR(SR_RX_CTRL + 0) // {now, chain, num_samples(30)
-#define FR_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1)
-#define FR_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2)
+#define U2_REG_RX_CTRL_STREAM_CMD _SR_ADDR(SR_RX_CTRL + 0) // {now, chain, num_samples(30)
+#define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1)
+#define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2)
-#define FR_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun
-#define FR_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter
-#define FR_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet.
-#define FR_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6)
-#define FR_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7)
-#define FR_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources
+#define U2_REG_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun
+#define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter
+#define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet.
+#define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6)
+#define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7)
+#define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources
//helpful macros for dealing with stream cmd
-#define FR_RX_CTRL_MAX_SAMPS_PER_CMD 0x1fffffff
-#define FR_RX_CTRL_MAKE_CMD(nsamples, now, chain, reload) \
+#define U2_REG_RX_CTRL_MAX_SAMPS_PER_CMD 0x1fffffff
+#define U2_REG_RX_CTRL_MAKE_CMD(nsamples, now, chain, reload) \
((((now) & 0x1) << 31) | (((chain) & 0x1) << 30) | (((reload) & 0x1) << 29) | ((nsamples) & 0x1fffffff))
#endif /* INCLUDED_USRP2_REGS_HPP */
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